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UCC27714: PIN #3, PIN #5, PIN #7, SHUNT RESISTOR

Part Number: UCC27714

Q1 : IS A JUMPER  USED TO CONNECT PIN #3 & PIN #5? ( AS SHOWN IN "Figure 54. Typical Application Schematic" ) 

Q2 : SHOULD A SHUNT RESISTOR BE USED BETWEEN PIN #3 & PIN 5 IN LIEU OF A JUMPER WIRE? ( SEE PIN FUNCTION FOR PIN #7 )

Q3 : IF A SHUNT RESISTOR SHOULD BE USED, WHAT WOULD THE CALAULATION EQUATION BE? ( SEE PIN FUNCTION FOR PIN #7 )

Q4 : IF SHUNT RESISTOR IS USED, THEN A 1-uF CAPACITOR SHOULD BE INSTALLED BETWEEN PIN #3 & PIN #7?

 

PIN FUNTION

PIN NAME :    VDD

PIN #         :     7
Bias supply input. Power supply for the input logic side of the device and also low-side driver output. Bypass this pin to VSS with typical 1-µF SMD capacitor (typically CVDD needs to be 10 × CBOOT). If shunt resistor used between COM and VSS, then also bypass this pin to COM with 1-µF SMD capacitor.

  • Hi Eddie,

    Q1: In Figure 54, pins 3 and 5 are directly connected through the PCB.

    Q2: Depending on the application, a shunt resistor or shunt ferrite bead between pins 3 and 5 may provide some benefit. A shunt resistor or shunt ferrite bead can be used to help decrease the effects of ground bounce or parasitic ringing which may couple into the logic ground.

    Q3: If using a resistor, this component should be selected to minimize the ringing that appears when measuring VSS with respect to COM. The procedure should look very similar to the one documented in TI's external gate resistor design guide, substituting CISS for the total capacitance to low-impedance nodes at this point (typically dominated by the capacitor between VDD and VSS). If using a ferrite bead, select the region of maximum impedance to minimize the interaction with the frequency of oscillation at the COM node. Keep in mind that if the shunt component between power ground and signal ground is the only connection point in the circuit between these two nodes, the average charging current through the low-side capacitor will be directed through these shunt components, with a corresponding voltage drop appearing across them.

    Q4: A 1-µF capacitor is only suggested because of the typical 1-µF capacitor between VDD and VSS. The precise value of the capacitor between VDD and COM should be selected similarly to how the value of the bootstrap capacitor is selected: the total capacitance should be large enough to prevent large fluctuations in the maximum LO output voltage, based on the gate charge of the load transistor and any additional output load (such as a gate-source resistor).

    Regards,