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TPS51116: how to current mode

Hayashi
Expert 1840 points
Part Number: TPS51116
Other Parts Discussed in Thread: TPS40140,

Hi team

My customer wants to know how to use to current mode
Please let me know the follow questions.
1.What is the minimum recommended by Vsense?
In the case of Rds (on) sense, Current limit is the value connected to 5 V => CS, and for 5 k it is set as the maximum value (OCP) such as 50 mV. What is the minimum recommended value at this time?
2.Are there any differences in this perception?
In the Current mode, even if parallel connection and ESR are made smaller, the phase compensation Margin is not affected. This is because in Cout = Ceramic, ESR is sufficiently small with respect to Ripple request. Therefore, the ESR of Cout is not included in the calculation formula of phase compensation.
3.Please tell me how to calculate Cout
In D-CAP Mode, there is a formula for calculating Cout minimum capacity, but it is not found in Current mode in particular.
There is a statement that Undershoot and Overshoot decide the Cout capacity in the data section of 9.2.2.4, but how do you calculate it?
Best regards
Hayashi
  • 0
    TI__Mastermind 24075 points
    Hello,

    1. For Rds(on) sensing, the current limit threshold setting range is from 30mV to 150mV. This spec "VR(trip)" is available on datasheet page 8.

    2. At current mode, when ESR is very small, there is no need for Cc2. This information is available on datasheet page 29, section 9.2.2.6.

    3. To calculate Cout at current mode, please refer to equation 22 and 23 on TPS40140 datasheet page 41.


    Thanks
    Qian
  • 0 in reply to Qian Chen
    Expert 1840 points
    Qian san

    There are additional questions.
    Please let me know follow questions.

    1. About RS recommended is to give 15 mV
    　　Quoted 9.2.2.3 Choose rectifying (low-side) MOSFET.
    Why does the device require a voltage of 15 mV or more?
    Please tell me which part of the current or voltage feedback is affecting this value.


    2.About reason of no restriction for low RDS(on), when using external resistor current sensing.
    　　Quoted 9.2.2.3 Choose rectifying (low-side) MOSFET.
    Why does the device no restriction for low RDS(on), when using external resistor current sensing?

    3.About the stability of phase compensation
    　　Quoted 9.2.2.6 Calculate CC2
    What is the stability of phase compensation, when using a ceramic capacitor with low ESR in the current mode?
    Is it better for ceramic capacitors than phase compensation margin when using electrolytic capacitors?

    Best regards
    Hayashi
  • 0 in reply to Hayashi
    TI__Mastermind 24075 points

    Hayashi-san, 

    1. As explained in datasheet, 15mV or larger ripple voltage promises smooth transition between CCM and DCM. 

    I think this restriction is from the accuracy of TPS51116 current sense amplifier.

    2. When external sensing resistor is used, the current sense is not related to Rds(on), therefore there is no restriction for low Rds(on). 

    3. If CC2 is used, CC2 and Rc together will create a pole and this pole can be used to cancel the zero from Cout and its ESR.

    The ceramic cap ESR is very small, the zero from Cout and its ESR is at high frequency region. Usually this zero will not affect cross frequency and phase margin. Therefore CC2 is not needed if ceramic cap is used. 

    Electrolytic cap ESR is larger. If the zero from Cout and its is at very low frequency region. It is an option to use CC2 to create a pole to cancel ESR zero. 

    It is not saying CC2 must be used. It is just an option. 

    For your design, I would suggest to keep a placeholder for CC2 and set it "not populated" in BOM. So you have choice to use CC2 or not based on test result. 

    Thanks

    Qian