Hi,
We are developing a lithum-ion battery management system using bq76930.
my understanding of DELAY_DIS bit in SYS_CTRL2 register is
1. If we set DELAY_DIS bit to 1 it will bypass the OV, UV, OCD, and SCD delay circuit and create zero delay(aprox. 250 mili sec) that means coloumb counter reading will be avilable after every 250 msec.
2. If we set DELAY_DIS bit to 0 it will take normal delay
PROTECTION 1 to 3 registers are use to set SCD, OCD ,OV, UV, delays.
my questions are
a. When I set DELAY_DIS bit to 1 what happens to fault bits in SYS_STAT register? Is it that, it ignores the delay settings of PROTECTION registers and updates all bits after every 250msec? OR all fault bits get ignored? OR when fault occurs corresponding bit is set high with ignoring delay setting?
b. What is normal delay? is it addition of all delays meaning, all bits in SYS_STAT registers will update after all delays provided in PROTECTION 1-3 registers(SOC delay, OCD delay, OV delay ,UV delay) ? OR is it that when fault occurs corresponding bit is set high after delay which configures in PROTECTION registers?
c. What is the behavior of delays which are configured in PROTECTION registers?
Please refer data sheet on below link
