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TPS543C20: GND pattern

K. Sasaki14
Guru 10200 points
Part Number: TPS543C20

TPS543C20 has PGND, GND and AGND pins.

How should we separate these GND?

I think VSEL, SS, RT, MODE, RAMP and ILIM pin resistor GND should be connected to AGND pattern and BP and VDD capacitor should be connected GND pin. Then GND pin and PGND is connected on inner layer.

Finally, AGND, PGND and GND should be connected at thermal PAD point as a one point GND connection.

However I think these GND connection are not separated definitely on EVM pattern.
GND of VSEL resistor etc... are connected GND pin pattern on the Top layer. And those are connected to GND pattern of Inner Layer 1.

Is not the way of these GND connection so severe?
Is it better to separate definitely?

Best Regards,
Kohei Sasaki

  • 0
    Guru 10200 points
    Hi team,

    I would be grateful if you could let me have your answer concerning this matter.

    Best Regards,
    Kohei Sasaki
  • 0 in reply to K. Sasaki14
    TI__Guru**** 191445 points
    Sasaki-san,

    The grounding is explained in teh layout guidelines section of the datasheet. On the EVM there is a separate large ground area on teh top side for the analog terminations. It is connected to the main PVIN plane layers (inner layer 1, inner layer 3, inner layer 4) and the large PGND copper pour area on the bottom layer by multiple vias. Yhis effectiely keeps the large circulating currents away from the sensitive analog signals.