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UCC28950: Delay between FET transistors not matching datasheet formula

Catalin Muntean
Intellectual 280 points
Part Number: UCC28950

Hi,

I am simulating in Tina TI the UCC28950 reference design which you can download from the product page and see that the delay between A and B (and hence also B and C) MOSFETs does NOT follow the formula the datasheet suggests.

Simulation delay between A and B FET --> ~440ns

Datasheet formula using RDELAB --> 5*RDELAB/0.26 (because ADEL is grounded) = 5*15.4k /0.26 = 296.15ns

Question: Is the datasheet's formula wrong or the SPICE model of the UCC28950 ?

Thank you !

  • 0
    TI__Mastermind 25570 points
    Hi Catalin
    The DS is more likely to be correct - We revised the DS formulae a while ago and it may be that the model was not updated. Please confirm that you are measuring the delays on the OUTx signals and not the delays at the respective MOSFET gates. The resistors on the IC set the delays at the controller and propagation delays - especially if there is any difference between those in the OUTA and OUTB (or OUTC and OUTD) paths will lengthen or shorten the delay.

    Finally, the Adaptive delays (ADEL) will modify the baseline setting (DELAB and DELCD) - can you check what you are doing with these pins. You can ground ADEL (and ADELEF) to defeat the adaptive delays feature.

    Regards
    Colin
  • 0 in reply to Colin Gillmor
    Intellectual 280 points
    I confirm I was measuring the signals at the OUTx pins.

    Also, ADEL and ADELEF pins grounded. Like I said above, I simulated the reference design from the UCC28950 product page, you can try it if you want.. but it will be a waste of time since I already did.

    I will trust the Datasheet then. Thank you and best regards.