TPS65381A-Q1: Behavior of ENDRV after abnormality detection

Hi Shinichi-san,

Another good reference that goes with Figure 5-15 in the datasheet is Figure 5-14 which shows the logic tree for both the ENDRV pin and the NRES pin.

 Q1) The ENDRV is turned off once after detection of abnormality, and then it is restarted.

                Is it necessary to set the ENABLE_DRV bit to 1 again after recovering from error?

                (In this case, bit at bit error is cleared to 0?)

 

                Or, if ENABLE_DRV was originally set to 1, as it is after return from abnormality

                ENDRV turns ON even if it does.

 

A1) If the detected error doesn't cause a state change through RESET or STANDBY state, the ENABLE_DRV bit will remain set and once the fault is gone the ENDRV pin can go high again assuming there is no further detected error that is in the logic tree that will force ENDRV low. So one example would be a transient OV for VDD5 regulator, while VDD5 is OV the ENDRV pin will go low, but once the OV on VDD5 is gone the ENABLE_DRV bit will remain set and ENDRV will go high again. Another example would be UV detection on VDD3/5, which will cause RESET state where both NRES and ENDRV will be low (see in Figure 5-14 that RESET state condition is another logic reason ENDRV will be low). After RESET state LBIST will run on the transition to DIAGNOSTIC state and the ENABLE_DRV bit will be re-initialized to 0 (assuming AUTO_BIST_DIS hasn't been set to 1, default is 0). See initialization source in the SAFETY_CHECK_CTRL register description, section 5.5.4.10 of the datasheet.  

 

Q2) On the other hand, in the Diagnostic mode, if ENDRV is set to ON, even if the WD abnormality occurs, it switches automatically from OFF to ON after returning.

What happens in the case of Active State?

 

A2) What happens with respect to the watchdog function in both DIAGNOSTIC and ACTIVE state depends on the configuration of the WD_RST_EN bit. The logic impact to ENDRV and NRES (RESET state) is seen in Figure 5-14 and impact to the states is in Figure 5-16. If the MCU fails to provide good events due to an abnormality in the MCU or software, the TPS65381A-Q1 will detect this as "bad events" or "timeout events" and the WD_FAIL_CNT will increment. When WD_FAIL_CNT increments to > 4 the ENDRV pin will go low, if the WD_RST_EN bit has been set to 1 and no further good events are received, the WD_FAIL_CNT will continue to increment to 7 +1 and this error will cause RESET state. In RESET state both NRES and ENDRV are low. After RESET state the ENABLE_DRV bit will be re-initialized cleared due to LBIST running on the transition from RESET to DIAGNOSTIC state (assuming AUTO_BIST_DIS hasn't been set to 1, default is 0). When DIAGNOSTIC State is entered WD_FAIL_CNT will be re-initialized to 5 so ENDRV cannot go low even if ENABLE_DRV is set to 1.

 

Q3) Will it be possible to prevent ENDRV from returning to H if it shifts to Safe mode after detection of abnormality?

 

A3) If an error is detected that causes SAFE state, ENDRV pin cannot go high. SAFE state is a global logic to prevent ENDRV going high. From SAFE state the device must transition to STANDBY or RESET state. In both cases eventually the state transitions will lead to DIAGNOSTIC state and the ENABLE_DRV bit will be re-initialized cleared (0) due to LBIST running on the transition from RESET to DIAGNOSTIC state (assuming AUTO_BIST_DIS hasn't been set to 1, default is 0). So there is no normal way that ENDRV can return H after SAFE state.

 

Best Regards,

Scott

HI Scott,

Thank you for your reply.

I'll share your comment with the customer.

If he has an additional inqury, I consult you again.

I appreciate your great help.

Best regards,
Shinichi