UCC24612: Startup mode question

Hello Gerrit,

Thank you for checking out TI's UCC24612 SR controller.

When the SR FET is off (at start up and during very light-load sleep mode) the intrinsic "body-diode" of the FET functions as the rectifier.  The diode shown across the SR MOSFET in Figure 13 (page 11 of DS) is actually the "body-diode" of that FET, so showing that diode along with the standard symbol of an N-channel MOSFET is kind of redundant.   Practically speaking, when the SR FET has no gate drive, you can envision that only the diode is there and the MOSFET and controller are "invisible".

As Vout rises from 0V during start-up, the SR controller receives power between its VDD and VS pins.  VD is a voltage-sensing input only and carries no current.  Once VDD-VS reaches the UVLO turn-on threshold (~4.5V), the controller provides gate-drive pulses to the SR FET and it no longer conducts through its "body-diode".   This scenario occurs the same whether the SR is located in the negative leg or the in the positive leg of the output winding.

The VS pin is always the "Return" of the controller, but is also part of the Vds-sensing arrangement, so VS should be connected as close to the FET source pin as possible to minimize parasitic inductance which can interfere with accurate Vds turn-off threshold sensing.   Similarly, VD should connect directly to the FET drain, to avoid including any stray inductance in the current carrying path to/from the FET.

I hope this clarifies the controller and SR FET operation.

Regards,
Ulrich