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LM25066A: Resetting the LM25066A, failure in data-sheet?

Part Number: LM25066A
Other Parts Discussed in Thread: LM25066

Situation is as following, the Overvoltage is set to 13,55V I increase input voltage to 13,6V, the output MOSFET is switched off. Input voltage goes back to 12,5V
Now I am pulling down EN/UVLO pin and  VREG for a 100us. And the output FET is not activating. I have designed on my board the reset circuit based on that what stays in the datasheet point:

8.4.5 Enabling/DisablingResetting
The SMBus address of the LM25066A is captured based on the states of the ADR0,ADR1, and ADR2pins(GND, NC, VDD) during turnon
and is latched into a volatile register once VDD has exceeded its POR threshold of 2.6 V. Reassigning or postponing the address capture is accomplished
by holding the VREF pin to ground.
Pulling
the VREF
pin low will also
reset
the logic
and erase
the volatile
memory
of the LM25066A.
Once
released,
the VREF
pin will charge
up to its final
value
and the address
will be latched
into a volatile
register
once
the voltage
at the VREF
exceeds
2.4 V.

So now after what I see for me the VDD pin should be pulled down not the VREG, maybe VREG only if you need chane or reassign the I2c address. I have looked on the scope at the VREG pin, it was 0,5 V for more than 300us, during the first 100us the Vreg cap is discharging linear down to 0,5V.

Is this a failoure in the datasheet or am I missing something?. Simple, The circuit is no starting on after Overvoltage has occured, even after proper resetting, regarding to the datasheet.

  • Hi Christopher,

    Thanks for reaching us on this. Can you please share more details of your system and specifications.

    Pulling the VREF pin low and then release will reset the logic and erase the volatile memory but it does not reset the LM25066A device. Toggling the UVLO/EN pin will reset the device from the latched-off state. Wondering, why this is not helping in your system.

    Are you checking on EVM or made your own circuit ? Can you share schematic and test waveform of Vin, Vout, EN, GATE, Timer, input current.

    Best Regards,
    Rakesh
  • This was done on my board, i will try to reproduce that on EVM.

    I am giving back honor to Ti  on EVM it works ok, after overvoltage event as soon as the voltage goes back to the nominal level  the output is self activated, even without resetting the LM.

  • Rakesh:
    Does the overvoltage event latch the LM25066 or only overcurrent?

    I have relative High Ohmic resistors setting the OVP and the hysteresis is very wide, the positive threshold is about 15V and negative about 8.5V.
    Does the circuit after over voltage event must go bellow negative threshold to activate the output? or when the VREF and EN/UVLO is pulled down it is does not matter. For example.

    Over voltage hysteresis is set as following
    OVP+15V
    OVP-8.5V
    now I set input voltage to 16V and output is switching off.
    Input voltage goes back to 12V.

    Should the circuit activate the output after releasing VREF/ EN/UVLO from GND?
    Or it must goes bellow the negative threshold point?

    This is VREF pin and after this the output was not activated. The procedure was so:

    VIN, 12V, outpout ON ,

    Vin=16V, output off (OK),

    VIN back to 12V,

    VREF to GND and the output still off (WRONG) . VIN did not go bellow 8.5 (Lower OVP treshold)
    This is VREF pin.

     .

  • Hi Christopher,

    The overvoltage event switches OFF the system but does not latch-off the device. The device resumes operation when the Vin is reduced below the OVP- threshold.

    Q) Should the circuit activate the output after releasing VREF/ EN/UVLO from GND?
    Or it must goes bellow the negative threshold point?
    A) the device can be reset with VDD or Vin power cycle.


    Best Regards,
    Rakesh