• State TI Thinks Resolved
  • Locked Locked
  • Replies 2 replies
  • Answers 1 answer
  • Subscribers 63 subscribers
  • Views 497 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

UCC28070: Clock Synchronization signal max duty cycle

shuang qiu
Prodigy 190 points

Part Number: UCC28070

Hi,

UCC28070 spec shows "Due to the influence of the synchronization pulse width on the programmability of the maximum PWM switching duty cycle (DMAX) it is recommended to minimize the synchronization signal's duty cycle." The max duty cycle is 50% typical, 0.2us min pulse width.

As we will use external clock sync function, please clarify the details influence. If the sync clock follow both 0.2us min width and 50% max duty cycle, whatever Dmax setting value, is it no issue absolutely? Thanks.

  • 0
    TI__Mastermind 34465 points

    Hello shuang qui,

    There is a limitation on the value of  RDMX (the max duty cycle ) when the UCC28070 is used with an external SYNC signal.

    There are 2 relevant equation in the datasheet shown below:

    DMAX (above) is the resultant max duty cycle when synchronised and this is not equal to the max duty cycle when synchronised.

    In equation 10 above fsync should be in Hz not kHz.

    So you will use equation 8 to set the RT value once you know the switching frequency and then you will use equation 10 above to set the RDMX value, the max possible duty cycle.

    Regards

    John

  • 0 in reply to John Griffin1
    TI__Mastermind 34465 points
    Hello shuang qui,
    I am marking this thread as closed since the necessary information was provided.
    Regards
    John