UCC24630: Confirm delay time for VSC disable function

Dear Masazumi-san,

Thanks for interested in TI's solution.
The VSC pin will sense output voltage after the DRV voltage is stable.
The SR disable voltage won't be trigger after the VSC sensing point.
It will need to finish this cycle and trigger it in the next cycle.

So basically, the delay is not caused by the delay time.
It is because it already pass the sensing point, and it will be trigger in the next cycle.


Best Regards
Kevin

Dear Masazumi-san,

1.For delay time you can count blanking time and sampling time as delay time. The VPC pin and VSC pin can use the same sampling and blanking time. For Rtblk=5k, delay time will be around 203ns+100ns=303ns. For Rtblk=50k, delay time will be 1us+100ns=1.1us.

2.Because the sampling time is 100ns, so it should keep below disable voltage for 100ns.

3.The larger the capacitor there will cause larger delay time on the VSC sensing


Best Regards
Kevin