TPS51206: VLH,min for VDD = 3.3V

That is unfortunate as that makes it very difficult to interface to 1.8V logic, like from an FPGA.

Can you connect S3/S5 to VDD (3.3V) via a pull-up resistor, then use FPGA to pull down S3/S5 to turn off TPS51206?

Thanks
Qian

I would prefer to not back-bias the FPGA even through a pull up resistor.

However, I think a low-threshold NMOSFET could be connected to solve this problem- connect the gate to 1.8V, and the source to the FPGA GPIO.
The drain is connected to the pull-up resistor to 3.3V.

This cascode arrangement will allow s3, s5 to go between 3.3V/GND, but the GPIO isn't back driven.

Hi Steve,

What's the GPIO pin high voltage?
If it is 1.8V with small variation, it should be fine to use GPIO pin to control S3/S5 directly.
The actual high threshold of S3/S5 is below 1.5V.

Thanks
Qian

The 1.8V has tight regulation, but without an actual threshold in the data sheet or commentary from the factory team about the threshold when VDD = 3.3V, I'm afraid on-paper I won't be able to justify it.

I agree with you it will work in real life, but the paper design wouldn't match up well and it would generate unwanted questions during the schematic review. :-)

Alternatively I suppose I could go back to the TPS51200- it has 3.3V parametric data, and indicated the enable threshold is 1.7V. But it is a much larger device and this is a very space constrained application- there are 3 TPS5120x devices on this board, so the area adds up quickly.