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BQ76940: BQ76940 alert pin

Lenna Yan
Intellectual 1960 points
Part Number: BQ76940

Hi,

When the battery is over charging or over discharging, the alert pin will toggle and trigger the interrupt. While the alert pin is also the interrupt indicator pin for the completion of current sampling. How to judge these two kinds of interrupts?

Below is the words on the datasheet.

Protection events will trigger toggling of the ALERT pin, as well as automatic disabling of the DSG and/or CHG FET driver (depending on the fault).

The conclusion of each reading sets the CC_READY bit, which toggles the ALERT pin high to inform the microcontroller that a new reading is available.

Best regards,

Lenna

  • 0
    TI__Expert 4640 points
    Hi Lenna,

    You would need to have the host check the registers in the bq76940 after each interrupt. See the datasheet to see which registers you need to poll to find out.

    Thanks

    Miguel
  • 0 in reply to Miguel Angel Rios
    TI__Intellectual 1960 points

    Thanks, Miguel.

    The host microcontroller can clear the corresponding status bit in the SYS_STAT register. The CC mode is set to always on. The status of SYS_STAT is 0x84, that is say current sampling is ready and the circuit triggered OV protection. The question is when write 0x80 to the SYS_STAT, the cc_ready bit can't be cleared, the SYS_STAT is still 0x84. Only writing 1 to cc_ready bit and OV bit at the same time can clear the cc_ready bit.

    the datasheet only tells writing 1 to the corresponding bit in the SYS_STAT register can clear the bit. If there are two bits set to 1 at the same time, is it impossible to just write 1 to one bit to clear this bit in SYS_STAT? 

    Best regards,

    Lenna

  • 0 in reply to Lenna Yan
    TI__Guru 54715 points
    Hi Lenna,
    You can write the bits individually or together. If the status register is 0x84 and you write 0x80, you should read back 0x04, but if CC_EN is high the read must be within the 250 ms or the status will go back to 0x84.
    Similarly if you write 0x04 the status register should read back 0x80. If the OV conditon has not cleared the status will go back to 0x84 again after the OV delay.
    If only 1 condition is cleared as mentioned above, ALERT will remain high. If the status register is 0x84 and 0x84 is written to it ALERT will go low. ALERT will go high again at the 250 ms scheduler interval if CC_EN remains set.