This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TPS659037: Power down sequence and Warm reset

Part Number: TPS659037

Hi all

Would you mind if we ask TPS659037?

<Question1>
In case of power down, according to main voltage down, the power down sequence will start.
Until VMAIN is less than VSYS_LO, should the power down sequence start to operate using RESET_IN or POWER_HOLD?

<Question2>
After starting PMIC, when nRESWARM is inserted, does the power remain?
According to BOOT1 setting, does RESET_OUT output again?
RESET_OUT from PMIC connects to AM574X's porz(F22),  the reset operation doesn't release?

Kind regards,

Hirotaka Matsumoto

  • Hi Matsumoto-san,

    1. POWERHOLD is preferable as it has no switch off delay. See Table 5-10 for a summary of the OFF requests.
    2. Power does remain, including RESET_OUT. See this previous post for more detailed description: e2e.ti.com/.../581699

  • Matsumoto-san,

    I have some additional clarifications:

    For power down, you can use RESET_IN or POWERHOLD to turn off the device. Kevin mentioned that POWERHOLD is preferred if you are using an enable signal to turn the device on and off. We do not recommend using VSYS_LO to turn off the device, since that will cause all power rails to turn off at the same time, rather that execute the power down sequence.

    For warm reset, the PMIC remains on. Any rails that are already on will stay on. Any rails that are off and part of the power sequence will turn back on in their designated order. By using the BOOT1=1 configuration, RESET_OUT will also toggle.

    A diagram of the warm reset power sequence can be found in the user guide: www.ti.com/.../sliu011f.pdf

    Thanks,
    Nastasha