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BQ40Z50: Discharge Termination Configuration

Sebastian Manz
Intellectual 470 points
Part Number: BQ40Z50


Hello,

I want to configure the BQ40z50 in a way that CUVC or CUV opens the FET when a defined remaining capacity is reached. The aim is to have a certain capacity reserve, which can not be accessed by the load. However it's also important to report 0% SOC before the FETs are openend, so the load can shut itself down gracefully. 

My questions:

1) I plan to use CUVC rather than CUV to define the XDSG threshold because I want the reserved capacity to be independent from the discharge current, and CUVC seems to respect the applied discharge current. Is this the best way to do it?

2) I'm not sure how to configure the "0%" threshold. The discharge termination voltage does not respect the load current. So in my view there are two possible ways: 

a) Set the discharge termination voltage to a value slightly above the point where CUVC will trigger while the max. current is flowing. --> Problem: With low currents I will have 0% reported too early.

b) Set the discharge termination voltage at "true empty cell voltage" and thus below the corresponding CUVC threshold and use "Reserved Capacity" for the desired reserve. --> Problem: The termination voltage will never be reached and FCC will never be updated, because CUVC triggers before. 

Are my assumptions correct so far? Which option would be the best one?

Thanks,

Sebastian

  • 0
    TI__Mastermind 42535 points
    Option b is the best. This is because setting a reserve capacity allows the IT algorithm to adjust RM and FCC so that you can still have some capacity at a reported RSOC of 0% to allow for graceful shutdown. Your Term V will always be higher than CUVC and the CUV thresholds. You can move them closer but still below the Term V. Configuring them with the thresholds higher than Term V is not advised for the same reasons you mention.
  • 0 in reply to Batt
    Intellectual 470 points
    During discharging, I want the (time or capacity) difference between the point where 0% is reported and the FET is opened to be small. The problem in a) is, that this difference varies with the load current, because Term V is fixed. This is why I considered b).

    Howver I didn't quite understand your suggestion.

    In a) I suggested setting Term V > CUVC and setting Res Cap = 0.
    In b) I suggested setting Term V < CUVC and setting Res Cap > 0. (trying to use Res Cap to compensate for the fact that Term V is not current dependant)

    You suggest Term V > CUVC and Res Cap > 0, which doesn't correspond to neither a) nor b).

    What I would take from your statement: After your concerns with setting Term V < CUVC it seems like I have to go with a) and live with it that when discharging with low currents SOC=0% will be reported 'long' before the FET is opened.

    Thanks,
    Sebastian
  • 0 in reply to Sebastian Manz
    TI__Mastermind 42535 points
    Why do you want to dsg up until the point where the FET opens? Your battery would typically be rated for a dsg upto 3V. In the presence of a high sustaining load, your available capacity will be reduced by the IR drop. So, until you hit terminate, you still have the ability to dsg. What keeping a reserve capacity allows is for a graceful shutdown and that you will still have some capacity left for a graceful shutdown after 0% RSOC is hit. To use IT algorithms ability to estimate capacity accurately, you need to have a term V which is above the lowest voltage to which the cell has been characterized. For Li ion cells that is typically 2.9 or 3V. Once you set Term V below it, it causes issues with gauging which you do not want. So, it is suggested that you keep Term V higher and set a reserve capacity to have the ability to shut down the system after dsg.
  • 0 in reply to Batt
    Intellectual 470 points
    I want to dsg up until the point where the FET opens because otherwise I would loose even more usable capacity. I have to open the FET at around 3.3 V (OCV) because there is (in this case) no other way of preventing the load from accessing the remaining capacity.

    Term Voltage should be set above the lowest characterized cell voltage --> I can fulfill this requirement.
    Term Voltage should be set above typically 2,9 or 3V --> I can fulfill this requirement.

    My load doesn't care what SOC is reported. However the reported SOC should be feasible in some way because the user can see it. I want the user to see that he has almost no capacity remaing when the dsg comes close to the point where the FET opens. That's why I want to set Term Voltage somewhere slightly above 3.3V + IR drop.

    If I set Term Voltage at such a high voltage value, will this mess up the gauging algorithm as well?

    Thanks,
    Sebastian
  • 0 in reply to Sebastian Manz
    TI__Mastermind 42535 points
    What is your chem ID? Send me your gg file, the value of your Rsns and your max load or IR drop and I can advise you better.
  • 0 in reply to Batt
    Intellectual 470 points
    The used chem ID is 0x2019. The max load is 2.7 A.
  • 0 in reply to Sebastian Manz
    TI__Mastermind 42535 points
    Thanks, expect to hear from someone on this post in a week.
  • 0 in reply to Batt
    TI__Genius 14985 points
    Hi Sebastian,
    The gauge will target reporting 0% at TermV + Delta Voltage + (however much it thinks is necessary to provide Reserve Capacity if ResCap is not 0).
    Delta Voltage is learned by the gauge based on the spikes it observes in your loaded voltage during the discharge. The purpose is to report empty before you hit Terminate Voltage so that in the worst case of another spike coming in it won't suddenly crash to below TermV and jump to 0%.
    If you set Reserve Capacity = 0 then it won't add any extra buffer. The purpose of Reserve Capacity is to allow you to have enough time for a controlled shutdown after reaching 0% if desired and if you know how much capacity is required to complete the shutdown.

    I'm not sure if I understand your issue well, so please try to rephrase it if I'm not addressing it properly. It seems like you should set Term V to just above CUVC. Typically CUVC is <3V and you can set TermV to 3V with no problem. The gauge will always be conservative and this sounds like your complaint. Can your system just report 1% to the user even if the gauge reports 0%, and then run all the way to CUVC?

    Unfortunately we have a very heavy loading at the moment and a number of folks are out of the office. We will still get to your files, but it might take another week.
  • 0 in reply to dMax
    Intellectual 470 points
    Hi dMax,

    I think that maybe I misunderstood how TermV works up until this point. I thought that TermV is compared to the voltage under load. So I thought that for example if TermV = 3,3V the SOC will be set to 0% if during discharge the cell voltage reaches 3,3V.

    But in your description ('set TermV to just above CUVC' (CUVC uses almost OCV)) it sounds more like TermV refers to an OCV value and the firmware checks if during discharge the corresponding OCV cell voltage would reach the value of TermV.

    Which one is correct? After this question is answered, I can go on and deal with the rest of the topic.

    Thanks,
    Sebastian
  • 0 in reply to Sebastian Manz
    TI__Mastermind 42535 points
    Hi Sebastian,

    No, Term V is not like an OCV value.

    In the presence of non zero reserve capacity we have the ability to use DOD to adjust remaining capacity to accommodate reserve capacity such that fcc=remcap+rescap+passed chg. This obviously is calculated from the cell voltage and subtracted from a zero reference that is provided by the Term V.

    Term V on a spiky dsg is also adjusted by the delta voltage.

    When you hit Term V, adjusted or not, the capacity goes to zero.
  • 0 in reply to Batt
    Intellectual 470 points
    Hi Batt,

    ok I think I understood.

    To rephrase the general goal:
    - I plan to use CUVC at a relatively high voltage (around 3.3V) to make the battery open the FETs with a defined amount of capacity left (reason is that we want a longer defined storage time even if the battery is "empty").
    - I want to set Term V in a way which provides somehow useful SOC output. The reported SOC should reach 0% slightly before CUVC triggers (at best, this would work with different discharge current values, but seems not like this is completely doable (I learned that Term V does not respect current dependant voltage drop))

    I will try your and dMax' suggestion and set Term V slighty above CUVC and then I'll see how the battery behaves.

    Since there are config files held out in prospect, I will not click "issue resolved" yet :)

    Thanks,
    Sebastian
  • 0 in reply to Sebastian Manz
    TI__Mastermind 42535 points
    Hi Sebastian,

    Your gg file config looks correct for a 4100mV charge voltage.
  • 0 in reply to Batt
    Intellectual 470 points
    Hi Batt,

    thanks for having a look at it. Yes, 4100mV is the intended charge voltage.

    However during testing with this config there seem to be problems. It looks like the prediction of FCC and True Full Charge E is not working as expected (by me at least) anymore. But first I need more tests to be able to provide helpful info.

    Regards,
    Sebastian
  • 0 in reply to Sebastian Manz
    TI__Mastermind 42535 points
    OK. Please reply back on this thread if you have data that you need me to look at.
  • 0 in reply to Batt
    Intellectual 470 points

    Hi Batt,

    I did a full cycle of charging CCCV and then discharging until the battery opens the FET, all while logging with BMStudio. All of the data is in the attached file T9.xlsx.

    To sum up:

    calculated delta of TrueRemQ after charging = 2653 mAh --> as expected

    calculated delta of TrueRemQ after discharging = 2608 mAh --> as expected

    TrueFullChargeQ after discharging = 2004 --> why so low?

    FCC after discharge = 2004 --> why so low?

    You can see that TrueFullChargeQ and FCC were even lower at the start of the test. The battery used for this test started with FCC values around 2700 mAh after manufacturing. Then it underwent several cycles, in which it was charged with constant current up to 16,4 V (no constant voltage phase) and then discharged until the FET opened. During the first cycles the FCC dropped (see LAD_ELA_T7.xlsx). Then in the next to last cycle it rose. Somewhere between the last rise and the start of this test here, the FCC dropped again. 

    What could possibly cause the (in my opinion) wrong values of TrueFullChargeQ and FCC (which also messes up the SOC values)?

    T9.xlsxLAD_ELA_T7.xlsx

    Thanks,

    Sebastian

  • 0 in reply to Sebastian Manz
    TI__Mastermind 42535 points
    Sebastian,

    From what I saw in the logs, I think that is an artifact of load. You are using Max Avg I last run with load select of 7. change it to 3. You'll get better results.
  • 0 in reply to Batt
    Intellectual 470 points

    Hi Batt,

    good suggestion. I'll try this.

    Thanks,

    Sebastian

  • 0 in reply to Sebastian Manz
    TI__Mastermind 42535 points
    Thanks for following up Sebastian.