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13S Application question

john xiao
Intellectual 470 points
Part Number: BQ77905

Dear all:

I use BQ77905 design 13S electric bicycle potection board,I have some questions:

1.The BQ77905 AVDD range of the chip is 2.1~ 3.25v. such a large error cause the error of temperature detection?

2.The BQ77905 Datasheet page25  recommended 13S schematic is from high to low 5+5+3 (high-end 5S, intermediate 5S, low-end 3S).If I design the schematic is from high to low 3+5+5,Is that OK?

3.do SCD test,I find the DSG output waveform will slowly descend until it reaches short circuit delay time and then quickly pull down to VSS.as below ,If add a diode(D2) to  VDD Pin, the voltage slow drop problem described earlier will not occur.the SCH as below

What is the bad effect of adding a diode to VDD?

4.in 13S Stack design,the Bottom BQ77905,Between The LD pin and Pack- is RLD,How to select the RLD resistance value?

  • 0
    TI__Guru 54715 points
    Hi John,
    1. No, the variation in the internal supply voltage is not a problem because the temperature thresholds are a ratio from the supply voltage which is used for VTB. As AVDD varies, VTB varies.
    2. Yes a 3 + 5 + 5 design should work. This will give more voltage for the FET drive on the bottom part but less for the the CTRC/CTRD of the middle part.
    3. During SCD the VDD will discharge through the filter resistor. VDD is the power supply for DSG, so once it falls enough that the output drops out of regulation, DSG will begin to drop. Using 5 cells on the bottom as in question 2 would provide more margin. The diode will hold up the VDD voltage and so also the DSG voltage. Concerns with the diode and holding up the VDD may be noise from the battery being rectified raising VDD such that it goes to customer test mode with shortened protection delays. Also an elevated VDD will raise the voltage needed on CTRC and CTRD.
    Similarly if there is a large load on the battery which does not trip an SCD but lowers the VC5 voltage by more than 10V for more than 50 ms, the part can enter customer test mode. If the load pulls down the battery voltage sufficiently that the upper CHGU and DSG allow the CTRC and CTRD to drop below VCTR2 for approximately 7 ms, the FETs may turn off. A resistor across the diode may allow you to adjust the time constant if needed.
    4. RLD should be selected to limit the current into the LD pin to a safe level, but also to adjust the PACK- voltage at which the part will see load removal. See the bq77905 data sheet paragraph 8.3.2.8 and figure 11. RLD will also have an effect with the ability of the system to automatically recover from a UV condition, see figure 24.
  • 0 in reply to WM5295
    Prodigy 30 points

    Hi VM:

    Thanks for you reply.

    About the 3+5+5 design(high-end 3S, intermediate 5S, low-end 5S),could impact CTRC/D signal strength across the stack.if modifying the RCTRC&CTRD resistance value,Can solve the signal strength problem?

  • 0 in reply to user5289909
    TI__Guru 54715 points
    Hi User,
    See www.ti.com/.../slua774 section 3 and figure 7. There is an input resistance to the clamp on the CTRx pins which will form a voltage divider with the external RCTRx. Decreasing the RCTRx value can maintain a bias current into the clamp, but it can't make up for the voltage margin of more cells. 5 cells operating in the 3-4V range would give VDD in the 15-20 V range and the FET outputs should always be in regulation. The same cells in a 3 cell configuration would give VDD in the 9-12V range and the FET outputs would not be in regulation but be at a level below VDD. See the bq77905 data sheet. As system designer you must determine if it is better to have the lower voltage on CTRx of a device where you should check that it does not drop out unexpectedly, or on the FETs at the bottom device where it could raise the RDSON of the FETs and lead to heating.
    While the data sheet has the recommendation you noted, you have likely also noticed that a combination of 4+4+5 would also cover the cell count with more voltage margin from the FET outputs.