This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TPS56C215: Maximum output capacitance

Part Number: TPS56C215

Table 5 in the TPS56C215 datasheet has a column "C_OUT(max)" = 500uF for my case (12V to 3.3V, 400kHz, FCCM, 10ms soft-start). This is not described anywhere else in the datasheet.

Is there a maximum allowed output capacitance for DCAP3 regulators?

My schematic has 1700uF on this output rail, placed all over the PCB. Some capacitors are behind ferrite beads. The startup current is 0.6A and should not be a problem. Is stability affected by the large output capacitance?

  • Hi,
    Because TPS56C215 is internally loop compensated, so it has maximum allowed output cap. Yes the output capacitance will affect the loop response. I can't give you a straight answer whether your loop performance is good enough. You can check the SW waveform to see whether the jitter is big, to see if the loop is stable. or you can upload your schematic and I will do bench measurement on the loop performance.
  • Thank you!

    Can more capacitance be added behind a ferrite bead filter? If yes, is there a rule of thumb how much the filtering has to be for the additional capacitance to become invisible for the regulator loop?
  • Hi Daniel,
    It depends on the location of your ferrite bead.
    1. the Vout sensing point is behind the bead. The bead can't make the additional capacitance invisible. It will introduce zero to the loop, therefore boost the phase margin.
    2. the Vout sensing point is before the bead. 1 Ohm bead around crossover frequency (around 1kHz to 50kHz) will make the additional capacitance invisible.
  • Thanks, nice explanation.