UCC28056EVM-296: AC Current Waveform explanation for burst mode

Hi Doi-san,

UCC28056 compares the COMP pin voltage to the burst-on and burst-off thresholds. When the COMP pin falls below the burst off threshold, the controller will provide 4 soft-off switching cycles and then stop switching. As there is no switching action, the PFC output voltage will begin to decrease. The internal error amplifier will then begin to slowly increase the COMP voltage as the PFC output decays. Once the COMP voltage has risen above the burst on threshold, the controller will deliver 4 soft-on switching cycles and then run with normal switching. Becuase the PFC block is switching again, the PFC output will start to rise above the nominal set point. The internal error amplifier will begin to decrease the COMP voltage. Once the COMP voltage has fallen below the burst off threshold, the controller will provide 4 soft-off switching cycles and then stop switching. This operation repeats as long as COMP falls below the burst-off threshold and rises above the burst-on threshold.

During the burst on, more current will be delivered to the output. This is why you see a jump in the input current at the same time the PFC output voltage rises and during the burst off period (when the PFC output is decaying) you see the current drop to a much smaller value. 

As you increase the load, burst packets are delivered more frequently to the output in order to maintain regulation. This is why you see the frequency of the large PFC output ripple increase as you move from no load to 0.8A load on the LLC. At 0.8A you are close to the edge of DCM operation and burst mode operation. As you increase the load further, you are moving further into DCM operation. At around 5A or so, you are moving from DCM operation into transition mode operation. 

Best Regards,

Ben Lough

Ben-san,

<1> Does switching to start mode or stop mode after 4 cycles of soft switching, depending on whether the repetition of the PFC basic switching cycle (around 10 μs) exceeds or falls below the burst threshold level of the COMP terminal?
 
<2> In this case, the AC input current observed as the input current waveform 1 to 3 sent yesterday (8/21) at the moment when it falls below the burst threshold level of the COMP terminal is closed several cycles from the continuous wave of the sine wave Is it a discontinuous waveform with a period?
 
<3> If the load factor decreases, the input current waveform means that the ratio of the break period to the repetition of the AC input current (sinusoidal) cycle increases, and the input current waveform 1 to 8 yesterday (8/21) Would you like to judge the data as valid (normal) behavior?
 
<4> Can you provide the reference current waveform and transition waveform to the soft switching cycle when there is a transition to the burst mode state depending on the load factor against the rated load, if there is waveform data available for reference?

Hi Doi-san,

1. Yes, moving between run and bstOFF states is dependent on COMP voltage. The COMP voltage to enter bstOFF state is 0.5V. The COMP voltage to enter run state is 0.625V

2. When COMP rises above 0.625V, the controller initiates 4 soft-on switching cycles and then resumes normal switching operation. The controller will continue to switch until COMP falls below 0.5V. When COMP falls below 0.5V, the controller initiates 4 soft off switching cycles and then stops switching.When in burst mode operation, you will see jumps in input current while the controller is switching and then very little current draw while the controller stops switching. This looks normal.

3. Yes, the input current waveform on slides 1 through 8 look normal.

4. Could you clarify what waveforms you are asking for. Are you asking for input current waveform and switch node waveform while in burst mode?

Best Regards,
Ben Lough

Hi Ben-san,

1.  In equation (67) in the UCC56301data sheet (Japanese), the share of the internal power supply share factor (Kvcrrmp) is
The left term of the calculation formula is converted to the right term so that it is in the range of 0.1 to 0.6, and C1, Cr, Iin, Icomp
The result can be calculated by substitution.
However, in this right term, C2 on the lower side of the voltage divider capacitor is omitted,
It seems as if it does not affect the setting of Kvcrrmp, but C1 = 150 pF, C2 = 0.015 μF
What is the reason for setting range of set C2 value?
 
2. As a countermeasure proposal for the problem that the output voltage drops in the previous answer mail.
I instructed a plan to change C10 from 0.015 μF to 6.8 nF, but the implementation result was not improved.
In our experiment, we changed the setting of C10 from 0.015 μF to 0.022 μF under the condition of R 14 = 1 MΩ,
Load change 0% (with 1 kΩ dummy resistance between 12 V output terminals) ⇔ 100% variation,
The burst operation at no-load is stable, and there is no drop below UVLO at Vcc,
There was no reduction in output, and there was improvement effect.
Is this setting reasonable? (Other evaluation board constants are default state.)
 
3. From the results of the above two items, it is said that the capacity setting of the evaluation board C2 = 0.015 μF is not the optimum value in item 1
Think about it, how can I check the optimal set values ​​of C1, C2 capacity on evaluation?
 
4. With use premised on load sudden change 0 ⇔ 100%, concerning the setting of C1 and C2 capacity values ​​in 1 above,
Please teach the proper range, or the way of thinking.

5. No explanation about Icomp in the datasheet.Is it same as Iramp in the table?

I am sorry. I mistake sled. Please delete above. Customer is busy about LLC. He has no time to check PFC at this moment.

Hi Ben-san,

Whether or not the burst time interval is normal is unknown because there are no waveforms on the evaluation board and data sheet.
Please provide me "Burst waveform of switch node and input current" which can see the time interval of burst operation.

In case of the UCC28056EVM-296 load is 0 mA, 10 mA, 20 mA, 25 mA, 30 mA.