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LMG1020: LMG1020 Power Dissipation

Masayoshi Takahashi
Intellectual 1530 points
Part Number: LMG1020
Other Parts Discussed in Thread: UCC27531, UCC27611

Hi team,

I have some question about power dissipation of LMG1020.

1. I think to calculate power dissipation of LMG1020, the customer will use equation below. (I found from datasheet of UCC27531) Is it correct? 

2. What is the 0.5 from? Othe GaN Driver don’t have 0.5 on equation such as UCC27611 below.

3. How much the ROL of LMG1020?

4. There is a difference of Roff equation. Which equation should we use ROFF=3 x ROL or ROFF = 2.7 x ROL? 

5. I think RGATE is externnal gate resistor. Could you tell me how to define in case of below?

Regards,

Yoshi

  • 0
    TI__Genius 12990 points

    Hi Yoshi,

    thanks for asking about LMG1020 on e2e! Im an apps guy who can help you.

    We know from Rja = 134 C/W with Tamb=25C Max power dissipation to reach junction temp of 150C is (150-25)/134 = 932mW

    To calculate power dissipation of LMG1020, we can use the total energy needed to switch the fet gate charge wrt voltage and frequency then divide this between all three internal driver impedance the gate resistor and the internal fet gate resistance. Where half the power dissipation consumed by the driver is during OUTH and the other half would be consumed by OUTL – the driver doesn’t supply dc current after the fet turns on so theres no dissipation and duty cycles does matter.

    Use section 2.7 http://www.ti.com/lit/ml/slua618/slua618.pdf

    We also have to account for internal driver current consumption using the avg current leaving the VDD cap times the VDD voltage. This heat consumption is smaller than gate driver losses, Ivdd operating typical current at 30Mhz is ~50mA with a 100pF load but this is with the 2ohm OUTH/OUTL. 50mA at 5V is 250mW which should be taken into account for worse case.

    R1 and R2 are for adjustable drive strength. They also limit internal driver shoot through. These resistors however do not need to be there and will only slow down the gate.

    RoH => from VDD-OUTH spec we know the max drop on OUTH will be 50mV @ 100mA or 0.5ohms max across temp

    RoL => OUTL similarly will be 36mV @ 100mA or 0.36 ohms max across temp

    the internal fet gate resistance can be found from the fet datasheet.

    please let me know if you have any more questions.

    Thanks,