Other Parts Discussed in Thread: TPS22975,
In my design the power on sequence will be happen as given below.
1) Enable will be in logic low state
2) VIN (+3V3) will ramp first. Ramp up time would be 2mS
3) VBIAS (+5V) supply rail will also start to ramp along with VIN. But it has 4ms as Ramp up time.
Does this power on sequence will create any impact on the IC performance?