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CSD13302W: Some parameters questions for CSD13302W

user4674678
Intellectual 490 points
Part Number: CSD13302W

Hi team,

I would like to use CSD13302W. 

Q1: VDS is12V. What is VDS voltage?  Does it mean the VDS voltage cannot be higher 12V for  CSD13302W?

Q2: What do the below  parameters mean?

td(on) Turn On Delay Time
tr Rise Time
td(off) Turn Off Delay Time
tƒ Fall Time

Would you provide a graph to explain these  parameters?

Q3: Can I use NMOS CSD13302W to switch a 3.3V voltage? Like the attach. 2pin is 3.3V/60mA input. 3 pin is 3.3V output. 1pin is controlled by MCU,

If this can be achieved, would you send me a correct circuit or a TINA circuit?

  • 0
    TI__Expert 7905 points

    Jun,

    Thanks for posting.

    Let em try to answer your questions:

    1. Vds is the allowed voltage from drain to source, if this voltage is exceeded the device will breakdown or go into avalanche, depending on the current/amount of energy this may damage or destroy the device. In practical terms the voltage will be a little higher than the 12V but 12V @ 25degC is all that we guarantee, like all MOSFET vendors.

    2. We have written a blog series here: , look for the blog in the section Understanding MOSFET datasheet and go to blog 5, switching parameters, in this blog there is a graphic and discussion on these parameters. In short, these are not good parameters to compare vendor to vendor and vary tremendously on the way the device is tested.

    3. In the diagram of the NMOS you have the body drain diode polarity incorrect. The Cathode of the diode needs to be connected to the DRain of the MOSFET, not the source. This means the drain and not source would be connected to the +3.3V. As long as the gate of the MOSFET is +ve with respect to the source the device will conduct, in the case of the CSD13302W the min voltage this needs to be is 2.5Vgs to guarantee the device is on with a certain level of resistance. If your MCU can provide a Vgs voltage of 2.5V then it should be fine, actual voltage MCU will need to provide will need to be ~6V as when the FET conducts will will be nearly 3.3V on the source , so 2.5V+3.3V is needed to keep the part on, if you do not have a floating gate drive pin to drive the gate of the FET. If this is not possible many people use pch devices in a configuration shown in the diagram below

    As for models, we provide device and not circuit models, the device model for the CSD13302W can be found here.

  • 0 in reply to Chris Bull
    Intellectual 490 points

    Hi Chris，

    Thanks for your reply.  I still quite understand. 

    Q1: I do not see "pch devices in a configuration shown in the diagram below".  Would you upload it again? 

    You mean I can use PMOS to achieve this function?

    Q2: I do a test circuit with TINA. S pin is floating in this circuit. D pin is 10V. G pin is 5V. Then I can get 10V in the S pin. 

    So, I can keep S pin be floating in the circuit to achieve this function, correct?

    I do another circuit, please check the below attach:

    I think this design is the better than S pin is floating. What is your suggestion?

  • 0 in reply to user4674678
    TI__Expert 7905 points
    Jun,

    I spoke with an application engineer and got the following response:
    If the customer wants the FET to block, the gate to source needs to be below the Vth and the source to GND impedance need to be much smaller than the equivalent drain to source impedance of the FET.

    For this case, you need to have Vg=0V, and source to GND impedance to be ~100kohm, like you have in the 2nd circuit