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TPS54394: PG condition when EN is Low

K. Sasaki14
Guru 10200 points
Part Number: TPS54394

Is TPS54394 PG pin high impedance when EN is Low?

If it is yes, please tell me the timing that PG pin becomes low. Is it the timing that VREG5 rises over VREG5 UVLO threshold?

Best Regards,
Kohei Sasaki

  • 0
    TI__Mastermind 19080 points
    Hi Kohei,

    Yes, I think you are right. The timing is the same as VREG5 rises over VREG5 UVLO threshold.
    When EN is low, the internal PGOOD FET is not driven to turn on, so PG pin is in Hi-Z state. Once the VREG5 rises over UVLO, the FET is turned on, and PG pin becomes low.

    Regards,
    Sam
  • 0 in reply to Sam(MPAA) Zhang
    Guru 10200 points
    Sam-san,

    Thank you for your reply.
    However I tested PG operation with TPS54394EVM, and PG was Low when EN was Low.
    I tested with EVM which was changed EVM's PG pull-up to VIN from VREG5.
    VREG5 turn on by EN becomes high, however PG is Low even though EN is Low and VREG5 is not turn-on.
    Which is right, your answer or my test result?


    Best Regards,
    Kohei Sasaki
  • 0 in reply to K. Sasaki14
    TI__Mastermind 19080 points
    Hi Kohei,

    Sorry for making you confused.
    I went to the lab and did a test. I pulled up the PG to an external +5V. I found, when the device was disabled, PG became low, which means the internal PG FET is still in ON state.
    This indicates the gate driver for this PG FET is powered from VIN, not VREG5.
    So, as long as VIN presents, the PG function will keep monitoring the Vout. If Vout is out of range, the PG FET will be ON and pull the PG down to Low.
    Hope the information is helpful.

    Regards,
    Sam