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UCC28711: Primary peak current and L primary

Jean Eddim
Prodigy 120 points
Part Number: UCC28711
Other Parts Discussed in Thread: TIDA-00173, UC3842, UCC28720, UCC28722, UCC28740, UCC28700

Dear sirs,

I´m involved in a new design including UCC28711. My design is a DC-DC flyback:

Input: 500VDC to 1300VDC

Output: 24vdc/0,2A (5W), Fmax= 80khz, eff=0,85

I am using the TIDA-00173 as a calculation reference.So the calculations are as follows:

DMAX = 1-DMAG-fmax * (Tr/2) . With fmax of 80khz, Dmax=0,5

Lpm = (2*Pout/eff) / IPPK2*fmax. So Lpm= 90mH

Ippk = 2*pout/eff*Vinmin*Dmax = 26mA

My questions are:

1) Can I use a much lower Dmax (i.e. 0,1) in order to get a much lower primary inductance. Any drawbacks?

2) With so low primary peak current (26mA) are there any drawbacks for designing/working properly?

3) My sensing resistor must be high (> 20 ohms) in order to ger a decent sensing voltage to the ic. Is it ok?

4) Is it better/easier/reliable to design for a higher output power specification?

5)  Is it better another controller/design, (UC3842...)?. I need isolated output, Please sugggest the most adequate controller

6) The circuit may be a Primary or a Secondary side regulation. Which is the best in this design?

Best regards

Jean

  • 0
    TI__Prodigy 750 points

    Jean,

    I think you will be better off using a BJT device.I recommend some changes to your design. The baseline design you are using is probably not the best choice for this. I would recommend that you look at PMP8678. In the referenced design, it is a 300VDC to 1000VDC design for 12W application and is designed using a UCC28720. You can change the design to a UCC28722 which has a larger base drive capability. HOpe this helps. I would follow this design as an example.

    Hope this helps

    VA

  • 0 in reply to VA Viswanathan
    Prodigy 120 points
    I do not see the reason to move to BJT design. My main requirements are not are fulfilled with your proposed components:

    1) Switch element must be designed for 2000 v aprox (1300v input + reflected output voltage + Vspike)
    2) There must be an isolation input-output. And I will design multiple outputs
    3) The Duty cycle Dmax, Lprimary, Primary peak current doubts are not answered in your proposed circuit (same calculations)

    Probably the TIDA-00173 is a better aproach?

    Please give more details, of your proposal in order to comply my requirements

    Thank you for your prompt answer. Best regards
    Jean
  • 0 in reply to Jean Eddim
    Prodigy 120 points

    Any updates?

  • 0 in reply to Jean Eddim
    TI__Prodigy 750 points
    1) Can I use a much lower Dmax (i.e. 0,1) in order to get a much lower primary inductance. Any drawbacks?

    You need >500ns of ON time for reliable operation. This means that you need atleast 5us of switching frequency across line and load before you lose regulation.

    2) With so low primary peak current (26mA) are there any drawbacks for designing/working properly?
    When the Gate turns OFF, the parasitic capacitance on the drain node needs to be charged. It is charged by the primary peak current. Assuming a 2K of voltage, 100pF of parasitic capacitance, for a 26mA current, the time it will take is 8us! Hence this puts some concerns on the switching frequency of operation and being able to transfer power effectively. This problem is marginally limited using BJT as the Collector to emitter capacitance is smaller

    3) My sensing resistor must be high (> 20 ohms) in order to ger a decent sensing voltage to the ic. Is it ok?

    As per the datasheet, just make sure that the value of sense resistance gives you the current sense threshold you need. Otherwise you should be fine as long as the resistance does not go into the Kohms

    4) Is it better/easier/reliable to design for a higher output power specification?

    For these requirements, I think it will be easier for you to design to higher power requirements. The design I suggested can be very easily adapted to isolated applications by sensing the primary side aux winding instead of secondary side.

    5) Is it better another controller/design, (UC3842...)?. I need isolated output, Please sugggest the most adequate controller

    I would recommend that you look at UCC28722, Or also at UCC28700 or the UCC28740.

    6) The circuit may be a Primary or a Secondary side regulation. Which is the best in this design?

    This will come down to your requirements for output regulation. In general, SSR designs will be more 'simpler' to work with but will come at the cost of the optocoupler.

    VA
  • 0 in reply to Jean Eddim
    TI__Prodigy 750 points
    TIDA-00173 would also work for your design. The power stage will need to be resized for your application. However the concerns mentioned in my previous email are also valid here with respect to turn OFF time and regulation
  • 0 in reply to VA Viswanathan
    Prodigy 120 points
    Thank you for your answer,
    Regarding turn OFF time, what of these actions do you consider will be a good approach (or indicate any other action)
    1) include a mosfet gate driver to increase gate charge current
    2) Select a mosfet with a low Cds / Coss (any specific series/manufacturer?)
    3) Increase Primary peak current by increasing minimum output current
    Any other asuggestion?

    Please add your comments to each option. Thank you
  • 0 in reply to Jean Eddim
    TI__Prodigy 750 points
    2) Select a mosfet with a low Cds / Coss (any specific series/manufacturer?)
    SInce you have a cascode drive arrangement ( if you choose TIDA-00173 as your base), you can get away with 2x 1000V MOSFET. You can use the ST 1000V MOSFET and they are good but choice of MOSFET will depend on your choice of reflected voltage and leakage performance.

    3) Increase Primary peak current by increasing minimum output current
    This will help you substantially.

    All the points you have mentioned are good. IN addition to what you have mentioned, you can also reduce the parasitic capacitance on the Flyback transformer. SOme ways to do that are sectioned Bobbin, reducing the number of layers etc.

    VA