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UCD3138: Double Zero Configuration Principle in Digital PID Coefficient Based on UCD3138

Part Number: UCD3138


Hello
I am currently studying your UCD3138-based full-bridge hard-switch development board. I am learning how to set the PID coefficient.

I read your application note "UCD3138 Digital ControllerControl Theory" on page 30 to learn how to configure the poles of the PID.The manual tells me that the two zeros are configured: To boost the phase by 180o, a 2 pole 2 zero compensator is needed and should be located at 1/10 of fc.

In the Fusion Design Offline software, I opened the bode simulation case of the UCD3138 full-bridge hard switch. As shown below:


The cross-over frequency of the system open-loop transfer function is approximately 4.7 kHz.

If the recommendations of the UCD3138 Digital Controller Control Theory are followed, the two zeros should be configured at 470 Hz, however, in practice, the two zeros are configured at approximately 8.1 kHz.

Why is this? What is the zero-point configuration principle of this full-bridge case?

  • The second pole placement position is recommended in the UCD3138 Digital Controller Control Theory: Place the second pole of the compensation at a frequency 10 times higher than fc to start with. This way it will not affect the expected gain and phase at fc.
    However, in the simulation model, the second pole frequency is about 20.7 kHz, but it is more than four times the crossover frequency fc4.7kHz, and it does not reach 10 times.
    This is why? What is the configuration rule for the second pole?
    We can see from the above figure that the configured system phase margin is only 29.22 degrees, obviously it is impossible to reach the minimum requirement of 45 degrees. Isn't the zero pole configuration in this simulation case bad?
  • Hi,

    The first zero needs to be lower than the crossover frequency to boost more phase. Maybe something is changed, and GUI doesn't show that. You can try the GUI, and move the first zero to right location in order to boost more phase.

    Regards,
    Sean