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BQ24295: Power consumption when not charging

Brian Krieger
Prodigy 130 points
Part Number: BQ24295

Hi, 

I am using the bq24295 charge controller with a single-cell 2900 mAh Li-ion battery and have been doing some testing with the evaluation board (part number BQ24295EVM-549). 

I am trying to make sure I understand a few of my test results correctly:

  • I connected my battery to the evaluation board then just let it sit on the table for about a week without charging or doing anything else to it - the battery voltage dropped from 4.14 V to 4.03 V. This seems like a lot of lost power and I'm trying to figure out whether this is normal or perhaps I have the configuration settings wrong somehow? In other words, are there configuration settings that impact the idle state power consumption of the application circuit?
  • I tried repeating the test with the IC disabled via the CE pin but the results were the same (this makes me think that it's not a configuration setting issue since I would assume that disabling the IC would minimize the idle power consumption)

Assuming that this level of idle power consumption is normal I am considering ways to improve the performance. One idea is to disconnect the charge control circuit from the battery via a mosfet or other switch when a charge source is not present. However, I have pull-up resistors to a 3V power rail on the I2C lines, and the I2C bus is in use (with the 3V rail active) even when the charge controller would not be in use. So, I'm concerned whether having those pins pulled up (via 10k resistor) to 3V when the bq24295 itself is not powered will cause any issues?

Thanks in advance for any advice or suggestions,

Brian

  • 0
    TI__Expert 8230 points

    Hi Brian,

    The bq24295 has an internal BATFET that connects the battery to the system output. The leakage on this FET has maximum current of 55uA, this means that if there's no other load connected to the battery or SYS, there will be a constant discharge current of 55uA.

    Brian Krieger said:
    I have pull-up resistors to a 3V power rail on the I2C lines, and the I2C bus is in use (with the 3V rail active) even when the charge controller would not be in use.

    If you have an LDO connected to SYS providing 3V for I2C pull-ups, this will increase the total standby current to 55uA + the quiescent current of the LDO (which usually is in the mA range). This would explain the capacity drop in your system.

    You can force the BATFET off when there's no adapter and the system shouldn't be needed, we call this ship mode and it's done by writing REG07[5] to 1. This will disconnect any load from SYS and reduce the leakage to a max of 20uA.

    The only way to turn the FET on again is either by plugging in the input, clearing the bit via the host (but I2C will be down if your pull-ups are powered from the BAT) or a low to high transition on the QON pin.

    EDIT: Wanted to add, on the 295 EVM, JP1 connects the BAT or SYS output to the on-board I2C pull-ups. Remove this jumper if you want to perform the test again.

  • 0 in reply to Fernando Lopez
    Prodigy 130 points

    Hi Fernando,

    Thanks for the prompt and thorough reply.

    From the EVM data sheet, it looks like there is no LDO, so I would expect standby current to be 55uA as you mentioned. However, I think a constant standby current of 55uA for 1 week would be about 9 mAh total, and I would not expect that losing 9 mAh from a battery with a capacity of 2900 mAh would lead to such a large voltage drop as I saw (4.14V to 4.03V). Are there any other standby current consumption mechanisms that might be present on on the EVM? I did not have anything else connected besides the battery.

    Thanks for the note about JP1 on the EVM - that is good to know. More generally, if I were to disconnect the BAT pins from the battery (for instance, just disconnect the battery from the EVM altogether) but still pull the I2C lines up to an external 3V rail via 10k resistors, would that be a problem (for instance, I have seen some ICs that can be powered via I/O pins even if VDD is not connected)? Thanks for your help,

    Brian

  • 0 in reply to Brian Krieger
    TI__Expert 8230 points

    Hi Brian,

    Brian Krieger said:
    From the EVM data sheet, it looks like there is no LDO,

    I was referring to whatever you are using to generate the external 3V rail for your I2C; typically it's an LDO.The device does have an internal LDO, REGN, but that's not what I was referring to. If you have anything at SYS, it will increase the current consumption. 

    On the EVM, if there's only battery, the extra leakage would be from the pull-ups on I2C from JP1.

    Have you measured the actual current flowing out the battery during test? 

  • 0 in reply to Fernando Lopez
    Prodigy 130 points

    Hi Fernando,

    Thanks for following up. I did measure the actual current draw out of the battery during test, and your comment about the current draw due to the pull-ups was spot on. Removing JP1 reduced the steady state current consumption drastically, from about 2.7 mA to about 34 uA (right in line with what you had said to expect).

    So, that is great news and I now understand why the test results I am seeing differ from what I had expected - losses due to the pull-up resistors on lines such as INT, CE, I2C lines, etc were responsible for the power losses I saw in my test.

    However, I'm still not sure how to proceed with my design. The IC is going to be on a I2C bus that needs to be active even when the charge controller is idle. This means that the SDA and SCL pins (and probably INT) will have pull-ups going to a 3V rail that is always active. However, when the charge controller is not being used, I need to figure out a way to have the IC not draw the ~3 mA of standby current via the pull-ups that I am seeing in these tests. Any ideas? Thanks,

    Brian

  • 0 in reply to Brian Krieger
    TI__Expert 8230 points

    Hi Brian,

    There's couple things you could try to help minimize overall quiescent current:

    • Increase pull-up resistance on I/O pins such as OTG, INT, STAT. These pins also have a pull-up resistor. On the EVM they are 10k, but you can probably increase them to 20k. 
    • Use a lower quiescent LDO like the TPS783 for your pull-up rail and using it as a 1.8V rail instead of a 3V - VBAT rail. This will reduce the current on the pull-up resistors.
    • Depending on the I2C frequency used (100kHz vs. 400kHz), you might be able to increase the pull-up resistor values a tad. Important thing here is not to violate the I2C specs. How much breathing room you have to increase the resistors will be a function of your devices logic level thresholds (typically between 0.3V and 0.4V) and your bus capacitance as well. This app note details the calculations for I2C pull-ups.

  • 0 in reply to Fernando Lopez
    Prodigy 130 points

    Hi Fernando,

    Thanks for following up. I will experiment with some of the options you suggest and see where I end up - I'll let you know if I have further questions. Thanks for your help and best regards,

    Brian

  • 0 in reply to Brian Krieger
    Prodigy 130 points
    Hi Fernando,
    Quick update for others who might be seeking to solve a similar issue - I found that if I have the pull-ups on the INT, I2C lines, etc going to an external 3V rail and not going to the SYS rail on the EVM, there is no measurable additional quiescent current draw. So, looks like the issue is with having pull-ups going specifically to the SYS rail and not necessarily having pull-ups at all.
  • 0 in reply to Brian Krieger
    TI__Expert 8230 points
    Hi Brian,

    Just to add to your INT comment: INT is an open drain pin. This means the leakage through the FET will be minimal, but there will still be some leakage when there's a pull-up resistor. Same applies to STAT.