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LMG1020: Gate resistors in low frequency use with high gate capacitance

Part Number: LMG1020

TI recommends using at least a 2 Ω resistor at each OUTH and OUTL to avoid voltage overstress due to

inductive ringing. Is there possibility to use 0 Ω gate resistor with 2 nF input capacitance with frequency 60 kHz?

Thank you and best regards

Mikko

  • Hi Mikko,

    Thanks for your interest in our part, my name is Mamadou Diallo, I will help address your concerns.

    Please find attached a selection guide written by my coworker Mateo that will help address your concerns.

    www.tij.co.jp/.../slla385.pdf

    Please let us know if you have further questions or press the green button if this helped solve address your concerns.

    Thanks

    Regards,

    -Mamadou
  • Hello Mamadou,

    My question related more suitability to use this drive LMG1020 with higher gate capacitance.
    LMG1020 datasheet previous version there was specified 1 nF rise and fall times but new version revised June 2018 they are removed.
    We use EPC2021 transistors in group of 16+16 and thus small gate drive with highest possible rise and fall times are required.
    Also minimum propagation delay is essential to avoid GaN body diode conduction in synchronous rectifier. Is there any reliability issues in peak current or power dissipation with LMG1020 low frequency use 60 kHz?

    Thank you best regards
    Mikko
  • HI Mikko,

    Thanks for clarifying. The transistor (ECP2021) in question is specified at total gate charge Qg (max) of 19nC.

    "We use EPC2021 transistors in group of 16+16"
    DO you mean by this statement that you're driving 16 in parallel? can you confirm how many transistors you're driving in parallel?

    Keep in mind driving the transistors with no gate resistor will lead to the total gate drive power being dissipated entirely in the driver.

    Though prop delay is a priority to you but that series resistor would help share that power dissipation given by the following equation:
    Psw = 0.5 x Qg x Vdd x Fsw x (Roff/(Roff+Rgate) + Ron/(Ron+Rgate)).

    Depending on the number of FET being driven we can estimate the power dissipation but typically we would recommend adding small gate resistor.

    Thanks in advance for the clarification.

    Regards,

    -Mamadou
  • Hello Mamadou,

    We drive 16 transistor at parallel 112 µΩ and we use at the moment 1 gate driver for 2 transistors. Is there any capacitive load limitation or just power dissipation. Can you check LMG1020 suitability for 1pcs and 2pcs EPC2021 transistor at the 60kHz without gate resistors.

    Thank you best regard
    Mikko
  • Hi Mikko,

    Thanks for clarifying those details.

    As it is I don't see any potential limitations with regards to power dissipation and load capacitance. According to my estimations, at 60kHz, the driver power dissipation will be equal to 52.4mW and should not be a concern for this device; and that is without any series gate resistor. The part is specified at 60MHz and the combination of low frequency operation and Vdd should even things out with the capacitive load.

    Please let us know if you have further questions or press the green button if this helped address your concerns.

    Thank.

    Regards,

    -Mamadou
  • Hi Mikko,

    in terms of driver losses when using EPC2021 @ 60k is not much.
    Check out section 2.7 from www.ti.com/.../slua618.pdf
    since Fsw is small, Vdrv is small, and total gate charge is also small the total power dissipation seen from the driver is not large.
    (15nC)(5V)(60khz) = 4.5mW x 2 EPC = 9mW
    Total power consumption available @ 25C amb temp is (150Tjmax - 25Ta) / 133.6 Rja = 935mW
    The total Trise for your driver is <2deg C so there should be no issue with driving 2xEPC2021 with one 1020 using no gate resistors

    thanks,