• State Resolved
  • Locked Locked
  • Replies 9 replies
  • Answers 1 answer
  • Subscribers 63 subscribers
  • Views 1157 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

UCD3138: IDE_KD problem

Merih Eren
Intellectual 440 points
Part Number: UCD3138

Dear all,

I was testing IDE_KD bit of FaultMuxRegs register of UCD3138. To test it, I configured DPWM0 and DPWM1. DPWM0 gets its duty from Filter and for DPWM1, CLA is not enabled. Both DPWMs are in normal mode.

DPWM1 duty configurations: 

Dpwm1Regs.DPWMPRD.all = 16000;
	Dpwm1Regs.DPWMEV1.all = 0;
	Dpwm1Regs.DPWMEV2.all = 0;
	Dpwm1Regs.DPWMEV3.all = 0;
	Dpwm1Regs.DPWMEV4.all = 16000; 	
With this configuration, I expect 0% duty cycle and continuous on DPWM1B.

To get duty of DPWM0, I configured Filter out clamp registers as:

            Filter2Regs.FILTEROCLPLO.bit.OUTPUT_CLAMP_LOW = 15520;
            Filter2Regs.FILTEROCLPHI.bit.OUTPUT_CLAMP_HIGH = 15520;

With this configuration, I expect 97% duty cycle.

I enabled both IDE for DPWM0 and DPWM1 and I set IDE_KD bit as 400. At the end, I observed the scope screen below where yellow is DPWM0A, blue is DPWM0B and green is DPWM1B.

My questions are:

- With this configurations, DPWM0A and DPWM0B pins are on at the same time which leads to cross conduction of two complementary FETs. Is there any method to eliminate this problem?

- DPWM1A has 0% duty cycle. How is DPWM1B duty calculated without any duty of DPWM1A? The reason why I am asking is this, it is written as "Db is calculated by Da (Filter Duty) times IDE_KD" in Technical Reference manual in page 233.

Thanks in advanced.

Best Regards,

Merih

  • 0
    TI__Mastermind 18370 points
    An expert will get back to you
  • 0
    Intellectual 440 points

    I now realized that if I clamp Filter outputs at most 15459, this faulty situation does not occur. But why, does it mean that I should not make my transistors on at 97%.

    Also, if I set IDE_KD = 5000, Filter output can be at most 15473. After that, again this situation occurs.

  • 0 in reply to Merih Eren
    TI__Mastermind 18370 points
    I am not sure. We will need to run a test in order to verify this. One of us will get back to you.
  • 0 in reply to Merih Eren
    TI__Mastermind 18370 points

    Please note, IDE_KD is in 4.9 qnote format, with the integer portion of the KD value ranging from 0 to 15 and 9 fractional bits.
    So the largest number that it can represnt is 15.99 ~ 16.

    If the sum of  (IDE_KD * FILTER_DUTY) + dead_time1 + deadTime2 is larger than the period, you will encounter a shoot through.

    So yes, depending on your dead times, you have to limit the (IDE_KD * FILTER_DUTY) not to exceed certain percentage of the period.

    Regarding DPWM1 that is conmfigured as open loop. To do IDE, you still need to connect to filter and have the output of filter to stay fixed at certain value to acheive open loop. In other words, CLA_EN in DPWM1 needs to be enabled in order for the IDE to function. DPWM1 still multiplies IDE_KD and FILTER_DUTY.

    FILTER_DUTY is dictated by the filter that is connected to DPWM1, there is no other way to force the value of FILTER_DUTY.

    Hope this makes sense.

    Regards,

  • 0 in reply to Yitzhak Bolurian
    Intellectual 440 points

    Hello Yitzhak

    It was really helpful. Thanks again.


    Regards.
    Merih

  • 0 in reply to Yitzhak Bolurian
    Intellectual 440 points
    Hello Yitzhak

    I configured my algorithm according to your explanation. However, there is one other problem. In my application, I use DPWM0 and DPWM1 and only one of them can use CLA. When the CLA transition is from DPWM0 to DPWM1, FILTER_DUTY value is around 15000 at the transition moment, where Dpwm0Regs.DPWMPRD.all is 16000. For transition, I first disable CLA of DPWM0, then I load corresponding preset values to Integrator and YN register. Then I wait till preset values loaded to corresponding registers. Then I enable CLA of DPWM1. What I expect after CLA transition from DPWM0 to DPWM1 is to have ~1500 at FILTER_DUTY register. However, previous FILTER_DUTY (15000) doesn't change and for 3-4 cycles, DPWM1 turns almost fully on (15000/16000). This makes me come to the main problem. Since FILTER_DUTY transition is not like what I expected, IDE_KD register exceeds the limits and again I encounter a shoot through.

    How can this problem be solved? Also, is there any suggestions to simulate this case without operating my application in order to protect my FETs from shoot through.

    Thanks in advanced.
    Regards.

    Merih
  • 0 in reply to Merih Eren
    TI__Mastermind 18370 points

    I am not sure if I understand your application.
    Why you can not use another extra CLA?
    Can you use CLAMP instead of (or in addition to ) filter preset? Till filter preset takes effect?

  • 0 in reply to Yitzhak Bolurian
    TI__Mastermind 18370 points
    If your concern was addressed, please set the status of this post as resolved.
    Regards,