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LP38693-ADJ: On power up, Vout has output even when EN signal held low.

Albert Lee83
Prodigy 60 points
Part Number: LP38693-ADJ

Hi All,

== ISSUE

On power up, Vout has output around 50ms even when EN signal has been held low.

== BACKGROUND

Currently using three (3) LP38693-ADJ chips on a board, all adjusted to 1.5V output, Vin is 3.3V.

EN signal is held low on power up and driven high when the FPGA on the board has finished loading the bitstream.  This signal from Oscilloscope looks good.

However, when 3.3V is powered up, the Vout has around 50ms output voltage around 0.5V for two (2) of the chips, and one (1) of them has an output of 1.2V for 50ms.

Two (2) of the LDOs are supplying power to the FPGA IO bank, and the other one (1) is supplying power to some 1.5V to 3.3V level shifters.

Please help this issue.

Thanks,

Albert

  • 0
    TI__Guru 55940 points
    Hi Albert,

    In order to help debug, could you please provide a multi-channel scopeshot with Vin, Vout, Ven, and Iout? Please set the time scale so that the startup waveform is maximized. This will help me see the relationship between the rails since I do not have access to your board.

    One thing to keep in mind is that since like most linear regulators LP38693-ADJ cannot sink current, if the output is biased high it will be up to the load to pull the output back down. I mention this because many times multi-rail loads can have internal paths such as ESD diodes that can provide an external bias to another voltage rail. As a debugging step, are you able to isolate the LP38693-ADJ from the FPGA to ensure that there is no bias being applied to the output?

    Very Respectfully,
    Ryan
  • 0 in reply to Ryan Eslinger
    TI__Guru 55940 points
    Hi Albert,

    Since it has been a couple weeks without a reply, I assume that this thread is resolved. If this is not correct, please feel free to post again.

    Very Respectfully,
    Ryan