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TPS22810-Q1: TPS22810-Q1 lealage current of UVLO pin

Tomohiro Nagasawa58
Expert 1570 points
Part Number: TPS22810-Q1

Dear Support team

(1)Seeing datasheet 5P,IEN/UVLO is max 0.1uA.(I think this is sink current)
Could you teach EN/UVLO pin voltage set up of this parameter test?

(2)My customer use Vin=3.3V,EN/UVLO=5V.
Is EN/UVLO current increase in this condition? If possible,please give internal equivalent circuit.

Regards

Tomohiro Nagasawa

  • 0
    TI__Genius 10855 points

    Hi Tomohiro Nagasawa, 

    Thanks for reaching out on E2E. Please find the answers to your questions below:

    1. The 0.1uA max is across all voltages on the pin (0V to 18V) on EN/UVLO. I looked at the characterization data and it does not vary much across voltage, so 0.1uA is a good maximum value.
    2. The EN/UVLO current does not increase in this condition.

    Please let me know if you have any additional questions!

    Thank you,

    Arthur Huang


  • 0 in reply to Alpha H
    Expert 1570 points

    Hello Huang-san

    Thank you for quick response.

    Seeing measured data in cutomer board,

    it seems that the current increases as the EN/UVLO voltage is raised and it has exceeded 0.1uA.(please see attached file)

    Could you guess this cause?

    ■Backgroud

    They are using under unusual conditions of Vin=3.3V and EN / UVLO=5V,

    so they are verifying that there is no problem.

    Regards

    Tomohiro NagasawaEN-UVLO pin current .xlsx

  • 0 in reply to Tomohiro Nagasawa58
    TI__Genius 10855 points

    Hi Tomohiro-san, 

    I checked our data again, even if VIN is lower than EN/UVLO I'm seeing much smaller current than your test results. How are you running your test setup and measuring the leakage current? 

    Thanks,

    Arthur Huang

  • 0 in reply to Alpha H
    Expert 1570 points

    Huang-san

    Thank you for kindly support.

    I am going to  ask customer to check test setup and measurement environment.

    Is it possible to provide your data and setup or simple equivalent circuit diagram of EN/UVLO pin to the extent that disclosure is possible?

    Please email below if possible.

    tomohiro_nagasawa@nexty-ele.com

    Regards

    Tomohiro Nagasawa

  • 0 in reply to Tomohiro Nagasawa58
    TI__Genius 10855 points

    Hi Tomohiro-san, 

    I ram some additional tests on the EVM, you are correct with your measurements.

    The datasheet and characterization data is spec'd with no output load. In this condition, the EVM was drawing about 0.05uA when the EN/UVLO voltage was 12V and 18V. I ran the same test again with a 3.9ohm resistor, and I was seeing ~0.28uA with the external load drawing around 800mA.

    Will this device still work for the application? Let me know if you have any questions.

    Thanks, 

    Arthur Huang

  • 0 in reply to Alpha H
    Expert 1570 points

    Hello Huang-san

    Thank you for EVM test.

    Current situation is that this device can be used in applications.

    Let me confirm more.

    (1) Is your test condition  Vin=3.3V with EN/UVLO pull down resister?

    (2) Looking at the customer's condition1,the cause of this behavior seems increasing leak current from EN/UVLO to Vout. How do you think?

    (3)During normal operation the voltage of the CT terminal is around 0V after the soft start period in actual waveform.  

    But seeing at the block diagram, it seems to maintain gate voltage after start-up after soft start. Was there any problem with this operation?

    Regards

    Tomohiro Nagasawa

  • 0 in reply to Tomohiro Nagasawa58
    Expert 1570 points

    Hello Huang-san

    I would appreciate if you could response my question.

    Regards

    Tomohiro Nagasawa

  • 0 in reply to Tomohiro Nagasawa58
    TI__Genius 10855 points

    Hi Nagasawa-san, 

    Apologies, I was working on other tasks. I realized I was running the PSU on the wrong settings the first time, so I re-ran my tests.

    After running the tests again, I am noticing different behavior when the resistor is attached vs not. 

    Without the external pulldown resistor, the current on the EN/UVLO pin was only 0.03uA, even when the EN/UVLO voltage was 12V or 18V. Please find my image attached to confirm.

    With the resistor connected, the EN/UVLO channel was drawing 1mA. Can you try removing the resistor in your setup and re-run the test?

    My bandwidth over the next few days is limited, I suggest the best way to test your situation is to get an evaluation module and test the configuration. This will help us understand the issue you're noticing. 

    Thank you,

    Arthur Huang

  • 0 in reply to Alpha H
    Expert 1570 points

    Hello Huang-san

    Thank you for response.

    We will consider checking with EVM.

    Could you guess the reason why the leakage current increases by adding a pull-down resistor?

    Regards

    Tomohiro Nagasawa

  • 0 in reply to Tomohiro Nagasawa58
    TI__Genius 10855 points

    Hi Nagasawa-san, 

    If the TPS22810-Q1 is on, then you'll have current going through the pull-down resistor, (12V / 10k).  This won't increase the leakage current, but some current will be flowing through the external pull-down resistor. 

    Thanks,

    Arthur Huang

  • 0 in reply to Alpha H
    Expert 1570 points

    Hello Huang-san

    Thank you for support.

    I got EVM and confirmed UVLO pin current under customer's condition. (Please see attached file)

    The result was not changed from 0.1 uA at 0 to 20 V.

    Based on this result, I'm going to ask customer to recheck measurement setup.

    If you have any doubts about the measurement results, please let me know.

    TPS22810EVM_UVLO pin current.xlsx

    Regards

    Tomonhiro Nagasawa