LM5069: Battery / Mains Power combination

Hi Aidan,

I will look into this and get back to you soon.

Best Regards,
Rakesh

Thanks Rakesh,
This looks like an ideal solution. However I am working with a 60V bus. Unless you suggest how the TPS2474x can be used at this higher voltage it does not seem suitable. The Sens pins will be well above absolute max. Or?
Aidan

Perhaps these 60V lines can be divided down and indeed other pins in a similar way, but this will significantly complicate the design procedure. Can you clarify that you are really suggesting this component as suitable in a 60V system?

In fact, I don't even think this would work. How could we get the gate voltage above the bus level. The charge pump would need to be supplied from 60v?

Please allow me to explain my situation more fully. My prototype is currently using my own discrete component design that implements most of the features of the LM5069 + Reverse current protection. However it is bulky and a little power hungry and will be relatively expensive to manufacture. Ideally I need a solution that is far more integrated and using a lot less components. I know that the LM5069 can support reverse protection with a few additional components, if I decide this is necessary.
Therefore I am asking if you can answer my concerns about how the LM5069 will operate under the conditions I outlined above. If it will perform without problems is would appear to be a better alternative to what I am using at the moment.

Hi Rakesh,

That's a very neat solution thank you. However I have been testing the solution using TINA-TI and instead of the LM5069 I have used the TPS2493. It does not include the insertion delay, which in the LM5069 is locked to the Timer for fault detection during in-rush. This meant that I was struggling to find a suitable capacitor size which satisfied both requirements. The feed currents to the timer pin are fixed and I was having to wait over 7 sec before I could switch on the device, due to the heavy inrush currents. Anyway.....the TPS2492 also has current monitoring and the separate Fault pin, which I have already used to drive the EN pin on the LM5050.

Having said this I have just hit a slight issue and I'm not sure if it is an error in the TINA-TI transient model for the TPS2493. Or if it is a problem with the datasheet description. Maybe you can help throw light on this for me.

In the datasheet for the TPS2493, it states that the PG (Power Good) output will be pulled low whenever the Vds of the external FET is below 1.25V for longer than 9mS. I see this exact behaviour in TINA-TI. But the datasheet also states that PG will be open drain whenever UVEN is low, Vds is above 2.7V, or UVLO is active.

Now I know this sounds like I'm being finickity, but exactly how are these states logically combined. In the simulator I have tested with the UVEN pin on one TPS2493 pulled low, but because I am sharing the Vout with another TPS2493 device, Vds of the first is less than 1.25V as my battery and mains inputs are within a few 100mV of each other. So which takes precedence? It seems the model suggests that the active state takes priority. But this perhaps does not make sense, as indeed I have UVEN low, which would rather strongly suggest that PG should never be pulled low under this condition. I mean, essentially why would you indicate PG when you have effectively disabled the IC!

Please can you confirm what is truly the case. Can I fully trust the model in TINA-TI?

I can probably overcome the issue with extra components...I'm still working on this. However my question still stands, maybe the datasheet is not entirely clear, maybe I misread it, maybe the model is wrong?

Can you tell me which?

Thanks again in advance.

Aidan

Hi Aidan,

Unfortunately, I did not get time to go through it in detail. I will look on Monday.
Can you please share the TINA-TI simulation file you are working on..

Best Regards,
Rakesh

TPS2493_LM5050_etc.TSCHi Rakesh,

I apologise it seems I was mistaken the IC does seem to operate as expected. Having said this I have attached my TINA-TI simulation file, which includes quite a bit of extra supporting circuitry. Some basic logic level prioritization of supplies, control lines from an MCU and simulation of standby control which removes the load during any period that neither controller is asserting PG. This is required to get the Vout up to nominal without constantly exceeding the power limiter on the pass FET. In reality this logic should be handled by the MCU, but here I kludged together a PMOS under control of the PG outputs that switches in and out the heavy load, just to effect the same thing.

If you could cast your eyes over this and perhaps point out any glaring errors, much appreciated.

All the best

Aidan

Hi Aidan,

Thanks for the simulation file. I did not noticed any mistakes in the schematic.
Any reason for selecting TPS2493 over LM5069 device?

Best Regards,
Rakesh

Hi Rakesh,

So I did mention the issue I was having with LM5069, regarding the settle timer and in-rush limiting timer being the same capacitor using different feed current, and not being able to control each seperatly. Maybe I was a little quick to abandon it. Still if you have any advise I would be interested to hear.

Having said this, I have gone further with the TPS249x. I started out trying the TPS2493, but then decided that the restart feature was just going to make management via an MCU more complicated. So I switched to the TINA model for the TPS2492.

Strange..... with exactly the same circuit configuration and by simply swapping the IC model. The TPS2492 model seems to have its PG pin reversed. I'm currently carefully checking this, but it really does seem that when VCC-VOUT drops to <1.25V the drain opens on the PG pin. This is the exact opposite behaviour to the datasheet and the exact opposite behaviour to the TPS2943 TINA macro.

Could you investigate, sorry I realise that I suggested an error like this before, but this does seem real.

I have attached a TINA model so that you can take a look, just try swapping the upper TPS294* model between 2942 & 2943 and watch the current "AM1" into the PG pin.

Thanks

Aidan

1727.TPS2493_LM5050_etc.TSC

Hi Aidan,

The PG_B response should be same for both TPS2492 and TPS2493. There is an error in the TINA-model. I will check with the modeling team to get it corrected.

One reason for LM5069 device recommendation over TPS249x is LM5069 has strong 230mA pulldown current and offers fast response during short circuit fault.

Best Regards,
Rakesh

Hi Rakesh,

Thanks for confirming the error in the model. Just as long as I know that the datasheet is correct then I can continue. In regard to the short circuit pull down current. The TPS2492 also supports 125mA protection pull-down. It seems quite adequate for my application. Therefore I think I will continue with this part unless I simulate and see problems so far this does not seem to be the case. 

Having said this I have developed the solution further and as a result I have discovered a few other parts of the design that I would appreciate your support with. 

1. The TPS2492 does not have a separate output that indicates the status of the OV/UV detect. In fact the UV pin as you are aware shares the function of an enable pin. The trouble with this for my design is that I need to detect the presence of correct supply voltages before I can make the decision to switch on the power. Because of this I must either design a discrete solution to detect input supply voltage and of course include in this some level of hysteresis. I only actually need UV detect at this stage and not OV protection as this would still be functional from the TPS2492. To avoid a discrete design I have used a TPS2400. Although I realise that this IC is designed to drive the gate of a external FET. In my design I have simply employed it in combination with an external zener to simply offer me a logic output from the power supply board that I can use to indicate the input condition to my MCU. No TINA model is available for the TPS2400, so I have had to roughly simulate this using a user defined voltage source. If the actual TPS2400 works in this configuration I am happy with the result. Could you confirm that the TPS2400 will work in this configuration. Please take a look at my TINA design to see what I have done. 

2. I wanted to have the initial inrush current from both my battery and mains supply to be current limited at a much lower level than the current limit implemented when the output has settled. I am never happy with any kind of in-rush current that rapidly charges the large capacitance that I have in my load, which could exceed 40000uF (Another reason being that I should only see current levels as set by the sense resistor, very intermittently, or under short, I would prefer not to stress my downstream supplies to such an extent if possible). To this end I have implemented the alternative in-rush control technique described in the datasheet. In this way as the output voltage initially rises I limited the in-rush current to just 3A max. This works well, however during a situation where a sudden switch between either battery to mains or visa versa this current limiting approach causes slows that charge of the pass FET gate, and therefore I would have to manage switch over under control of the MCU which complicates matters further. Therefore I have added some extra control circuitry that floats the capacitor on the pass FET gate, thereby effectively only power limiting the pass FET current under such a condition where either of the ORing controller show an active PG condition. It relies on monitoring the PG output of either ORing controller, and if either shows an output voltage that in within the PG threshold it floats the gate capacitor and will rapidly charge the gate and allows a smooth switch over between power sources. Could you comment on the technique I have used and confirm or otherwise that this can be considered as an acceptable solution.

I apologise for the rather complex configurations within the TINA file. Many controlled sources are used to simulate as best I can the MCU actions. I don't expect you to waste your time on these aspects of my design. But it would be very helpful if you could address the 2 points above.

Will it be possible to get hold of an updated TINA model for the TPS2492, although not critical you will see that I have simply inverted the output from the PG pin, but this simulation is not 100% accurate as it is not open-drain. However I think it is probably effective.

Again I thank you for your help and look forward to further comments.

Aidan

TPS2493_LM5050_MCU_logic.TSC

Hi Aidan and Rakesh
We have added the TPS2493 model to our queue to have the PGdelay corrected and same as TPS2492. Please let us know if the TPS2492 needs any change as well.
Thanks
Ranjani

Hi Ranjani,
Actually I think it is the TPS2492 that needs correcting. When I was using the TPS2493 model it seems to pull low when active and lets go open drain when inactive. From what I could see the delay seemed correct. But when I replaced the model with the TPS2492 this presented the opposite behavior on the PG pin. It seemed to be active - open drain and inactive - pulled low. I did not check the delay, but this was a more fundamental issue.
I would be pleased, if a little embarrassed if this is not the case, but I do believe this to be the case.
Aidan

Hi Aidan
Thanks for the correction, we will work on fixing the TPS2492 model delay. We are looking to have it completed in 3 weeks.
Ranjani