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UCC28951-Q1: UCC28951-Q1

Part Number: UCC28951-Q1

Hello

How did you set that 155ns in the page nmbr:51 of UCC28951-Q1 datasheet . please explain the following those two conditions mentioned in that page number for Tabset 

and also for Tafset condition where you have taken 170ns as the cutoff . 

Thanks !

  • Hello sir 

    please let me know the answer for the above asked question by me.

  • Hello Rajashekar

    I've been out of office for the past while so please excuse the delay in this reply.

    At the top of P50 of the UCC28951-Q1 DS it states that the Adaptive delays are actually fixed rather than being truly adaptive. The schematic being used is NOT the one shown in Fig 52 rather the one shown in Figure 1 of http://www.ti.com/lit/an/slua560c/slua560c.pdf (below). I realise that this is confusing and I would suggest that you read slua560c to understand how the ADEL and ADELEFpins are being used.

    The fixed delay approach was described by the original designer of the circuit for simplicity. Normally the ADEL and ADELEF pins are used as shown in Fig 52 of the DS. Many of the variables involved in finding an optimum setting for these adaptive delays are dependent on circuitry outside of TI control so an iterative approach is suggested.

    Please note that the ADEL pin shortens the delay time as the CS signal increases. The ADELEF pin increases the delay time as the CS signal increases.

    1

    Please let me know if you need any further information.


    Regards
    Colin

  • Hello Colin

    I did not get what i have asked the question earlier .

    How did you set that 155ns in the page nmbr:51 of UCC28951-Q1 datasheet . please explain the following those two conditions mentioned in that page number for Tabset 

    and also for Tafset condition where you have taken 170ns as the cutoff . 

     Thanks

    Regards 

    Rajashekar

  • Hello Rajashekar

    The 155ns value comes from the range of delay values available by using the resistor at DELAB (RAB) and DELCD (RCD) pins if you set the ADEL pin to a fixed 0.2V (155ns to 1000ns) or a fixed 1.8V (29ns and 155ns). These limits can be calculated as the extremes where 13k Ohm <  RAB or RCD > 90k. You can see in Fig 29 and Fig 30 that the delay range available if ADEL is tied to 0V is 250ns to 1750ns. So, the designer has used a DC bias at ADEL and ADELEF to modify the programmable delay range. The DC levels at ADEL and ADELEF of 0.2 and 1.8V are those used in the electrical characteristics table earlier in the datasheet, but other DC values could be used too.

    Although the UCC28951-Q1 offers the flexibility of having adaptive delays the designer in this case chose not to use this feature and to instead use the ADEL and ADELEF pins to extend the range over which he could program the delays. You can see below that the 170ns value for Tafset requires a 90k resistor at DELEF which is at the upper end of the recommended range. Adding a DC level to ADELEF will increase the range of delays available. Normally if adaptive delays are not used the ADEL and ADELEF pins should be tied to GND where their effect is zero (KA = 0 in the graphs Fig 29, Fig 30 and Fig 32 and Fig 33). The effect of tying the ADEL and ADELEF pins to a fixed non zero voltage via a potential divider off VREF is to apply a fixed offset to the delays. 

    The notes below may make it clearer.

    WITH ADAPTIVE DELAYS:

    Choose Tabset and Tcdset according to eq 146 and 153 (eg 346ns). Use RCD = RAB = 18k using eq 151 (KA = 0) and tie ADEL to a potential divider, initially with 0 Ohms to GND.  

    Choose Tafset and Tbeset to 50% of Tabset or 170ns. This is recommended in the DS at the top of P53. Use REF = 90k (eq 6) and tie ADELEF to a potential divider, initially with 0 Ohms to GND.

    These delays should allow initial testing to proceed and final optimised delays to be selected.

    NO ADAPTIVE DELAYS: 

    Use the same approach as above except with a permanent connection to GND for ADEL and ADELEF.

    The main issue here is that it isn't really possible to predict in advance what the optimum delays should be and the designer has to iterate to a solution.

    Please let me know if you have any further questions.

    Regards

    Colin