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TPS659037: TPS6590379

rekoe
Intellectual 895 points
Part Number: TPS659037

Hello,

The data sheet shows that the signal RESET_IN is low or high active. where can you control that and in which default state is it?

  • 0
    TI__Genius 10000 points

    Rekoe,

    The RESET_IN polarity is OTP dependent. You can find the default OTP settings in the user guide: http://www.ti.com/lit/pdf/sliu011

    For the TPS6590379, the default is active low. If you wanted to change the polarity, you could use the POLARITY_CTRL register to update the RESET_IN polarity. Note that any time the device is restarted, it will start in its default state (active low for RESET_IN). You would have to change the polarity each time the device turned on, after all the rails finished powering up.

    Thanks,

    Nastasha

  • 0 in reply to Nastasha
    Intellectual 895 points

    >> The RESET_IN polarity is OTP dependent. You can find the default OTP settings in the user guide: http://www.ti.com/lit/pdf/sliu011

    Thank you, the TPS6590379/TPS659037 has the OTP (Softwareversion) 0x97.

    That has to follow that SMPS7 and SMPS9 are working.

    I dont understand correctly the boot0/1 pin´s.

    with boot0 I can select the generated voltage von SMPS3 between voltage level of 1,35V and 1,5V.

    But what does boot1?

  • 0 in reply to rekoe
    TI__Genius 10000 points
    Rekoe,

    BOOT1 selects whether the RESET_OUT signal toggles during the power sequence. This is enabled by pulling BOOT1 high. It is recommended for the AM57xx processors, that BOOT1 is pulled high to resolve one of the processor erratas (i862).

    Thanks,
    Nastasha
  • 0 in reply to Nastasha
    Intellectual 895 points

     Hello,
     
     Do I have to pull up Boot1 to use PMIC.RESET_OUT -> AM57xx.porz correctly?
     I think independently of BOOT1, PMIC.RESET_OUT will toggle to high on power up sequence.
     Will PMIC.RESET_OUT toogle with Boot1=high at the time of an warmreset event?

     What about the difference between RESET_OUT and POWER_GOOD?
     RESET_OUT will toggle to high if the power-up sequence has been completed. But are the voltage levels checked? What happens if one LDO has a fault like a short circuit?
     
     Does PWGOOD just check voltage levels on the SMPS?
     
     
     In my application I don't want to use any switches or buttons to reset / switch-on the devices. Are the following HW-settings correct?
      - PWRON is floating
      - RPWRON is floating
      - nreswarm <- AM57xx.reset_out
      - nsleep is floating
      - boot1 = high; boot0 = low (because ddr3_lp is used)
      - enable1 is floating
      - gpio7 is pulled up
      - gpio0..6 are pulled low
      - pgood and reset_out are combined with a logical AND function
      - RESET_OUT -> AM57xx.porz

  • 0 in reply to rekoe
    TI__Genius 10000 points

    Rekoe,

    It is recommend that BOOT1 is pulled high for correctly generating a POR on the AM57xx devices. With BOOT1=1, RESET_OUT will toggle on power sequence and warm reset.

    POWERGOOD will go high when SMPS12 goes high, and go low when SMPS12 goes low. You can configure POWERGOOD to monitor other SMPS rails too if desired. POWERGOOD does not monitor LDO voltages. RESET_OUT does not check the voltages. It goes high when specified in the power sequence. It will stay low if there is no ON request.

    If a SHORT occurs on any rail, the rail affected will shut off. If the short is cleared, the rail will turn on with a POR or by reading the SHORT STATUS register.

    I also recommend using Figure 3 of our user guide to verify your HW settings (http://www.ti.com/lit/pdf/sliu011). I recommend pulling NSLEEP up to VRTC. Also, GPIO7 (POWERGOOD) pulled high will have the device set in an always-on state. You should ensure you have a way to disable the device. TI doesn't recommend using loss of power to disable the PMIC since the power down sequence will not be correctly implemented.

    Thanks,

    Nastasha

  • 0 in reply to Nastasha
    Intellectual 895 points

    Hello Nastasha,

    thank you for your answer.

    If I have connect the PMIC and processor like figure 3 on (http://www.ti.com/lit/pdf/sliu011) :

    The NRESWARM is connected trough a voltage level converter with RSTOUTn from processor.

    At the time on starting up the pmic, the processor is in reset. That has the consequence the the RSTOUTn (processor) is low and that signal is on PMIC NRESWARM.

    Is the NRESWARM ignored while waiting for it to go high?

  • 0 in reply to rekoe
    Intellectual 895 points
    A TPS6590379 has always the OTP version 0x97 ?
  • 0 in reply to rekoe
    TI__Genius 10000 points
    Rekoe,

    All TPS6590379 have OTP revision 0x97.

    When starting up the PMIC, RESET_OUT will go high once the power sequence is complete. When RESET_OUT goes high, a warm reset will not be triggered until NRESWARM sees a falling edge. After a falling edge is detected, NRESWARM is level sensitive and will continue to generate a warm reset until NRESWARM is high again.

    This pattern repeats anytime RESET_OUT goes high. Otherwise, NRESWARM will remain level sensitive.

    Thanks,
    Nastasha