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UCC28056: The layout of Rdg

chentsu chung
Mastermind 6180 points
Part Number: UCC28056

Hi,

From datasheet I know RDG needs to be placed between DRV and GND.

But the situation now is, the layout mistake result in RDG connected from RDG to Rcs (source pin of MOSFET).

May I ask what will happen in the situation?

1. Will it affect the performance of valley switching?

2. If yes, then it should affect IC that reading the delay time setting in startup, and won't affect anything else during the normal operation, am I right?

3. Is this only affect the performance of valley switching?  If not, what is the others?

Thank you very much.

  • 0
    TI__Mastermind 27145 points
    Hi Chentsu,

    Thanks for your interest in UCC28056. The Tzcdr delay is set by the resistor setting from DRV to ground. The Tzcdr is selected during startup or when recovering from a long fault and then the Tzcdr does not change during normal operation.

    1. It is possible to see some effect on the valley switching. I would not expect the a large change because the current sense resistor is typically a low resistance but you may see some change in valley switching performance

    2. The Tzcdr delay setting is selected during startup or when recovering from a long fault condition. During normal switching operation, the Tzcdr setting does not change.

    3. I would check the ZCD/CS pin waveform to make sure the coupling between DRV and the ZCD/CS pin is not affecting the waveform shape. A distorted ZCD/CS pin waveform can lead to incorrect MOSFET timing or erroneously tripping on the protection functions such as OCP or OVP2.

    Best Regards,
    Ben Lough