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Original question:

BQ76930: BQ76930 : state of REGOUT in SHIP mode

BQ76930: BQ76930 : Schematic validation

Cyril HAENEL
Prodigy 130 points
Part Number: BQ76930


Hello,

I develop a 20 cell BMS, and I will be happy if you could validate my BQ76930 schematic part, it is attached :

schema1.pdf

Some explanations :

- I want the BMS to be very robust and idiot proof, thus the 20 cells are managed with 2 indepedant BQ76930, which are galvanically isolated between them, and also galvanically isolated from the host MCU electronics part. Thus on the schematic, you will find only 1 BQ76930 to manage 10 cells, the other 10 cells management will use exactly the same schematic (I will have 2 I2C interface on my host MCU).

- The GND reference for the BQ76930 comes directly from the negative of the 1st cell of the 10 cell chain it manages (CELL0 / GND/1 on the schematic)

- Current measurement/protection will be done directly with the host MCU, thus SRN/SRP are not used

- Temperatures measurement will be done directly with the host MCU, thus TS1/TS2 are not used and are pulled low with 10K resistor

- I used N channel mosfet for the external balancing, to avoid stress on the BQ76930 during random cell connection if P channel activates and pull too high some input of the BQ76930 (as explained in the slua749a.pdf document)

- I use the REGOUT output to supply the isolated part of the I2C isolator chip. To avoid permanent consumption on the pack when it will be OFF, the host will send the SHIPMODE command to power down the BQ76930, and shutdown the REGOUT output (as you confirmed me in a previous question I asked)

- The BQ76930 will be activated during each pack startup with the BOOT signal on TS1 input, using and optocoupler to isolate from the host MCU output

Would be great if you can validate the schematic, because schematics of eval board or datasheet are not easy to read and understand. And we have shrt delay, would be great if everything can work the firt attempt :)

I really want to have a robust design, don't hesitate to suggest some more protection component if needed, to be sure the random cell connection during connector connection will never burn something.

  • 0
    Prodigy 130 points
    Also, CHG and DSG are not used because the host MCU will drive these mosfets

    Thank you very much for your help

    Regards
    Cyril
  • 0 in reply to Cyril HAENEL
    TI__Guru 54715 points
    Hi Cyril,
    It seems you have been very thoughtful with the design.
    ALERT is both an input and output. The pull down resistor and a cap across the pull down may avoid noise coupling into the pin as an input, but it may not be a concern to you since the FET outputs are not used.
    While the part is intended to take random cell connection the large difference in filter capacitors can impose a high voltage stresses on the part in connection. You might look at figure 21 of slua749, the VC10B and VC11 inputs are the ones I have heard that have been damaged. These are the lowest single ended voltage abs max of the inputs. In your situation you might also consider if VC12 or the VC12 to VC11 differential voltage is a concern. When using differential zeners remember that the inputs will go to 1.5x normal voltage when the adjacent cell balances.
  • 0 in reply to WM5295
    Prodigy 130 points

    Hello WM5295,

    Thank you very much for our prompt answer !

    For the ALERT in/out, I added a small cap to GND to avoid noice coupling. But you are right, I don't use FET output thus it's not really a big concern.

    When you talk about the large difference in filter capacitor, what can I change to improve the design ? DO you talk about the difference between the 0.1µF cap for input filter and 10µF for VC5X and VC10X ?

    For the figure 21 of slua749, VC10B and VC11 are mentioned, but I don't have these inputs in my design with the BQ76930. But I suppose there is the same concern for VC5B and VC6 in my design ?

    Differential zener can be a solution but I need to verify if the leakage current is not a problem, it is not uncommon to see leakage currents of 100µA or more

  • 0 in reply to Cyril HAENEL
    TI__Guru 54715 points
    Hi Cyril,
    "When you talk about the large difference in filter capacitor, what can I change to improve the design ? DO you talk about the difference between the 0.1µF cap for input filter and 10µF for VC5X and VC10X ?"
    Yes, when a voltage is applied to a series of 0.1uF and 10uF, most of the voltage will appear across the 0.1uF capacitor. With the device architecture it is difficult to change the capacitor values much. The zener is one solution but has the risk of leakage as you indicate. Connection order is another possibility.

    "For the figure 21 of slua749, VC10B and VC11 are mentioned, but I don't have these inputs in my design with the BQ76930. But I suppose there is the same concern for VC5B and VC6 in my design ?"
    Yes, the same condition will occur at VC5B and VC6.