Hi,
I'm looking at Figure 10 on page 8 of the datasheet, which is the radiated EMI scan.
I'd like to know the test setup - i.e. cabling, and is it a 2-layer PCB with a ground plane?
Also, if I needed to reduce the radiated EMI by 20 dB in the 700-900 MHz range (I need < 10 dBuV/m) , how would I do it?
Right now I can meet EMI with my current buck converter designs (12V->5V and 3V3) either by adding an RC snubber to the switching node or adding a small resistor in series with the bootstrap (hi side driver) capacitor to slow down the upper FET turn-on.
The LMZ21071 is attractive due to the PCB footrpint area savings.
TIA