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TPS7B4253-Q1: Enable vs ADJ

Part Number: TPS7B4253-Q1

Hi Team,

I noticed in the TPS7B4253-Q1 datasheet that there are two different packages, one that has an enable pin (HTSSOP) and the other only has a adjust pin (DDA). For the HTSSOP package offering with the enable pin, it say that the enable is used to put the device into a low power standby state. Is that a state that can only be achieved by using the HTSSOP package OR can the DDA package offering produce the same standby state with the adjust pin?

Thank you,

Jared

  • Hi Jared,

    The pin functions state that the ADJ pin on the DDA package can be held low to disable the device. Voltage thresholds for ADJ pin low are listed in the Electrical Characteristics table: Adjust low signal valid. This will put the device in DDA package in a low power state. See graph in Figure 7 for shutdown current.
  • Hi Jared,

    The standby state is only available with the HTSSOP (PWP) package as this state allows for the IN and ADJ rails to be valid without allowing the device to have an output.  You can disable both the DDA and PWP packages by pulling Vadj to GND.  When disabled the DDA package should have the same typical shutdown current as the PWP package when Ven and Vadj are tied to GND.

    Very Respectfully,

    Ryan

  • Hi Ryan,

    What is the purpose of the EN on the HTSSOP package? Basically, what do you get out of having the IN and ADJ pins as valid with the output disabled? Does it just mean faster startup time?

    Thanks!
    Jared
  • Hi Jared,

    Yes the advantage of the EN pin is that both IN and ADJ pins can be at their final voltages before enabling the output voltage. Since the reference is already at its final value OUT can rise quicker. In a traditional linear regulator, the ramp rate of OUT is limited by the ramp rate of the internal reference.

    Very Respectfully,
    Ryan
  • Excellent, thank you for the details!