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TPS3813: TPS3813 power up

Damien_Effi
Intellectual 555 points
Part Number: TPS3813
Other Parts Discussed in Thread: TPS3823, TPS3851, TPS3850

Hello,

I connected WDT to VDD and WDR to ground. The reset output is connected to the MCU Reset.

When I switch on the system, there is a reset every 3s after TPS3813 power up. However WDI stayed always low to be sure the watch dog is not running during  MCU programming.

According to the datasheet :"After the first WDI low-to-high transition is detected, the lower boundary function of the window is enabled". So, if WDI is low, the watchdog should not start.

Am I right? If yes, why the watxchdog is starting?

Thanks for your support,

Damien

  • 0
    TI__Genius 12630 points
    Damien,

    Unfortunately, the watchdog does not disable by holding WDI low. The watchdog still has the upper window frame, even though there has not been a low-to-high transition on WDI. The WDI low-to-high transition enables to lower boundary, but the device still resets at 3s because this is the upper boundary.

    If you need the watchdog to be disabled during power up, you will need to switch to a device such as TPS3850 (or TPS3851) or TPS3823.

    I hope I answered your question, please let me know if you have any other questions. Thanks!

    -Michael
  • 0 in reply to Michael_DeSando
    Intellectual 555 points

    Hi Michael,

    Thanks for the clarification.

    Damien

  • 0 in reply to Michael_DeSando
    Prodigy 170 points

    Hello,

    I wonder if you could please clarify the operation of the open-drain reset output? Assuming VDD is within the acceptable threshold, and there has been at least one valid transition on the WDI pin but the WDI driving source then fails to continue toggling the watchdog input of the device, would the RESETn output hold low, or would it continue to only pulse low every few ms or secs, depending on the window timing configuration?

    Many thanks.

  • 0 in reply to Stephen Serlenga
    TI__Genius 12630 points
    Stephen,

    The /RESET output will trigger for the reset delay time then come back high until the next watchdog timeout expires and no valid WDI pulse will cause the /RESET output to trigger low for the reset time delay again. So the output will continuously drop low for the reset delay and go back high again until another missed pulse. This is the output operation when a watchdog fault occurs. When the VDD is causing the fault due to undervoltage condition, the /RESET output remains low the entire time until the voltage comes back up then the reset delay time expires then the /RESET output comes back up.

    I hope this answers your question. Please let me know if you have additional questions. Thanks!

    -Michael
  • 0 in reply to Michael_DeSando
    Prodigy 170 points

    Dear Michael,

    Thank you for your response; it helps clarify the device operation. 

    My application requires a watchdog device that holds (latches) low until the system gets a hard-reboot. I also do not need the supply monitor aspect of the device, so I think there may be much more suitable devices in your catalogue for my particular application.

    Kind Regards,

    Stephen