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Original question:

BQ77915: RCTRx Minimum Value

BQ77915: Resistor placement on the LD pin with 8S stack configuration with MOSFETs on the + side

Qiwang Zhang
Prodigy 20 points
Part Number: BQ77915

We are currently working on a project involving BQ7791500pw, and saw an issue of load detection during OCD, OCC testing. It turns out that we forgot to place the resistor on the LD pin. Upon reading some documents, I realized that all the samples had the MOSFETs placed on the negative side. We had the MOSFETs placed on the positive side. Our question is this, for the load detection to work properly with MOSFETs on plus side, how do we place resistors at the 2 LD pins. Can we simply connect the top LD pin to the GND for top 4 cells, and connect a resistor of 470kOhm at the bottom stack from LD pin to B-? Thanks.

  • 0
    TI__Guru 54715 points
    Hi Qiwang,
    It can become complex. We don not have a recommended circuit.
    As you have observed in the data sheet, the LD pin has a comparator at 1.3V across the low side FETs and a 200k pull down when attempting recovery.
    If you are using high side switching it is typically because you have some circuitry inside the battery you want to communicate with. If that circuitry includes an MCU, the MCU could control the bottom LD pin with an output. For an upper part the MCU would need a level shifter to B+ if it needs to hold off the upper part from recovery. Of course the MCU does not know the state of the bq77915 and must infer the condition from history and sensing various inputs available which might include FET states, battery and pack voltages.
    If there is no MCU a suitable control may require more circuitry. The upper part will not have current protection, so its LD does not need to move for OCD or OCC. The -00 configuration part requires load removal for UV recovery. If the upper LD is connected to its GND and it is the device which experienced the UV, it will recover when the voltage comes back above the UV hysteresis.
    The bottom part uses LD for current recovery, its polarity needs to be opposite the movement of PACK+. LD will pull low and may need to be held high to hold off an OCD recovery. LD must go above the 1.3V threshold to recover from an OCC condition. A transistor might be used as an inverter referenced to an intermediate voltage. Certainly bias currents should be minimized and leakage paths avoided.