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UCD3138: UCD3138 CLA DELAY ONE MORE QUESTION

jun yin
Intellectual 875 points
Part Number: UCD3138

Hi Sir:

We update the event As soon as Filter calculation is done, while we found Pulse extension issue;

The delay for the CLA (between SAMPTRIG and Filter Output) is about 450 nS. For UCD3138 the event update window is by default 75 nS from the start of period.

we set SAMPTRIG and output clamp high by taking all this into consideration; we can sure if CLA delay is 450ns, Event update window is 75ns, there is no chance that moving edge of DPWM would go into event update window;

we adjusted the SAMPTRIG and found the CLA delay was around 250ns; is there any way we can measure the CLA delay directly to confirm this?

  • 0
    TI__Genius 17090 points
    I'm not aware of any easy way to measure the CLA delay. I have in the past figured out a very complex way to look at the CLA delay. I am pretty sure that it is more than 250 ns. More like 500 ns, depending on how you measure it. Note that if you start doing averaging, the delay actually increases.
    And there is some jitter as well, because the EADC is not synchronized with the sample trigger. When the sample trigger comes, the filter starts the next time the EADC produces a sample. So there is a jitter of either 64 or 128 ns nominal.

    We recommend running the DPWM with the UPDATE_SEL set to 0, meaning start of period. If you do that, it doesn't really matter when the CLA finishes. I believe that the filter output is shadowed, so even if it changes during the update, there should be no issue. The values being put into the DPWM will not change.
    What topology are you using, and how is the shoot through occurring?
  • 0 in reply to Ian Bower
    TI__Genius 17090 points
    Since no response, I'm going to assume that selecting the update_sel set to 0 resolved the issue.