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CCS/UCD3138: Front-end DAC RAMP setup

Part Number: UCD3138

Tool/software: Code Composer Studio

Hello there!

working on a totem-pole PFC project with UCD3138,

I am having trouble setting up the front-end DAC ramp.

My issue is that the DAC value which I read from the DACSTAT register does not increase, and instead stays stuck at its initial load value (the beginning of the ramp).

Besides, the RAMP_BUSY flag stays at '1'.

Here is an extract of the code I use :

FeCtrl0Regs.EADCDAC.bit.DAC_VALUE 		= 100; // ramp start value
FeCtrl0Regs.RAMPDACEND.bit.RAMP_DAC_VALUE	= 1000; // ramp stop value
FeCtrl0Regs.DACSTEP.all 			= (10 << 10) + (0 << 9); // ramp step value
FeCtrl0Regs.RAMPCYCLE.bit.SWITCH_CYC_PER_STEP 	= 0; // 1 switching cycles per step
LoopMuxRegs.FECTRL2MUX.bit.DPWM2_A_TRIG_EN	= 1;
FeCtrl0Regs.RAMPCTRL.bit.RAMP_EN		= 1;
FeCtrl0Regs.RAMPCTRL.bit.FIRMWARE_START 	= 1;

Can someone kindly help me find the reason to that issue ?

Thanks a lot!

  • Seems like you are missing the following statement/configuration:
    LoopMuxRegs.FECTRL0MUX.bit.DPWM2_FRAME_SYNC_EN = 1;
    Please note that without linking DPWM to Front End and having the Frame pulse advance the ramp counter, the ramp mechanism with never ramp up.

    Hope this resolves the issue.

    Regards,
  • Yes, thank you this resolves my issue.

    In fact, I believe the following statement becomes useless :

    LoopMuxRegs.FECTRL2MUX.bit.DPWM2_A_TRIG_EN = 1;

    am I right ?

  • It depends,

    Sample trigger is still needed for commanding samples in the EADC.

    If DPWM2 is the only DPWM that is commanding samples from EADC, then you still need the above statement.

    If any other DPWM/s triggers samples from FE0(EADC0), then you may not need this specific one that connects DPWM2 to EADC0.

    Regards,

  • OK,

    well I guess I misunderstood how the sample trigger works then, because I thought that the below statement was sufficient for triggering FE0 with DPWM2 :

    LoopMuxRegs.SAMPTRIGCTRL.bit.FE0_TRIG_DPWM2_EN = 1;

    isn't that correct ?

  • Your understanding is perfectly fine.
    LoopMuxRegs.SAMPTRIGCTRL.bit.FE0_TRIG_DPWM2_EN = 1;
    is enough.

    But UCD enables triggering of EADC from more than one source/DPWM. Only if more trigerring required.

    Regards,
  • Hello,
    OK I got it, thank you.

    Now I see another problem related to the previous one :
    the voltage between EAP0 and EAN0 pins has an additional 10mV offset, all the time BUT when the front-end DAC is ramping up.

    so 2 questions :
    _ why do I get this offset when the front-end DAC is not ramping up ?
    _ is there a trick - related to UCD3138 configuration - to cancel it out ?

    Notes :
    1/
    FE0 is triggered by DPWM2 all the time.

    2/
    I checked whether it comes from the hardware before EAP-EAN pins, and it does not.
    EAP0 is driven by an op-amp followed by a 1k-2.2nF RC filter. Before the 1k resistor I see no offset.

    3/
    AFE_GAIN is set to 3.
    if I decrease AFE_GAIN, the "base offset" increases as expected (as specified), however the "additional offset" decreases, down to zero for the AFE_GAIN=0 setting

    4/
    the "additional offset" appears only on the EAP0 pin. EAN0 only has the "base offset"


    Well, thank you for your guru insights on this !

  • Are you sure that the offset exists both before and after the ramp, but goes away during the ramp up? Please double check.

    Please also use a 100 Ohms resistor instead of the 1KOhms resistor (You can increase the Cap value to get the same level of filtering) and see if it helps.

    Do you have a Cap in the feedback path of the op amp?

    Regards,