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Original question:

BQ40Z50: Learning Cycle Issues

BQ40Z50: Learning Cycle | Update Status not changing to after final discharge rest

Zander Nevitt
Prodigy 220 points
Part Number: BQ40Z50

Hello,

I am trying to complete a learning cycle for my single Samsung1.5 Ah NMC power cell with a BQ40z50 EVM board. After a few initial hiccups, I was able to work through all of the steps outlined in this learning cycle guide and everything was going as expected up until the post C/5 discharge rest period when Update Status never went to 06. It has been stuck at 05 since the post charge rest period. Interestingly, QMAX and the Resistance Table for the cell have updated, and my Cell0 R_a Flag is now set to 5555. I believe these three things indicate that the learning cycle was successful, but I’m not sure because Update Status is not 06, as the learning cycle document says it should be.

My question is this: Why is my Update Status not going to 06? Does this indicate that my learning cycle was not successful, even though QMAX and Resistance tables are updating?

An outline of the steps I am taking from start to finish can be found here.

A register log file for the learning cycle can be found here. The discharge data being around 13:00 on 10/10/2018. The associated error log can be found here.

A data memory gg.csv file from right before the C/5 discharge was started (end of post charge rest period) can be found here.

A data memory gg.csv file from midway through the C/5 discharge can be found here.

A data memory gg.csv file from immediately after the C/5 discharge completed can be found here.

A data memory gg.csv file from 12+ hours into the C/5 discharge rest period can be found here.

Please let me know if you have any specific questions, or if more data would be helpful, as I have many more gg.csv files I could share.

Thank you,

-Zander

  • 0
    TI__Genius 10830 points

    hi Zander,

    I wanted to let you know that your post has been assigned to one of our applications engineers. This week takes place our annual Battery Management Deep Dive event for which all our engineers are all hands on deck. He will be able to your post early next week, once this event is over.

    You can check out recordings of much of the material we present at www.ti.com/deepdive

    Thank you for your understanding!

  • 0
    Prodigy 220 points

    All,

    We were not reading an update status of 06 after completing the 5+ hour rest after the C/5 discharge referenced in section 4.2.6 of the Learning Cycle document we have been using. We went ahead and tried to charge the battery to full again at a rate of C/2 and then during the rest period after this charge the Update Status finally went to 06. 

    However, after this post charge rest period, we then discharged the battery again at a C/5 rate, and let it rest over night. When I came in this morning the update status was still at 06, not 0E as is referenced in the last point of section 4.2.6 of the learning cycle document. 

    Question: Should our Update Status now be 0E? Or since we are only using a single cell, is 06 correct? If we should be seeing an Update Statue of 0E, what steps should we try to get there?

    Thank you,

    -Zander 

  • 0 in reply to Zander Nevitt
    TI__Mastermind 42535 points
    Zander,

    Update Status after 2nd dsg will only change to 0E if you do not have RDIS set when you dsg. If it sets at any point you will not get an update to 0E. Also to get 0E, you need to have VOK clear at the end of dsg after relaxation. If you have logs for this cycle, send them and we can take a look.
  • 0 in reply to Batt
    Prodigy 220 points

    Thank you for your response.

    Here is the .log file that starts from just before starting our post learning cycle C/2 charge. Here is a data memory log from that same time. 

    Here is a data memory file from the middle of this learning cycle. 

    Here is a data memory file from directly after stopping the C/2 charge.

    Here is a data memory file from right before starting the post learning cycle C/5 discharge. 

    Here is a data memory file form right after stopping the post learning cycle C/5 discharge. 

    Here is a data memory file from 5+ hours after stopping the post learning cycle C/5 discharge.

    Please let me know if any more data would be helpful.

    Also, does the fact that the update status only went to 06, and not 0E, indicate that the learning cycle for this single cell configuration was unsuccessful? It does appear that the resistance tables were updated, some I am unclear as to what the 0E status tells us.

    Thank you very much for your assistance. 

    -Zander 

  • 0 in reply to Zander Nevitt
    TI__Mastermind 42535 points
    Zander,

    Do you still need help on this issue? A status of 0x0E indicates that Qmax and Ra have been learned and optimized. A learning cycle with Qmax updated would get to 0x05, a discharge following that would get to 0x06. A second chg-rel-dis-rel cycle would get you to 0x0E after which the pack is said to be learned and optimized.
  • 0 in reply to Batt
    Prodigy 220 points

    Yes, this answers my question. Thank you!