Other Parts Discussed in Thread: EMB1412
My client's BMS uses the 1499/1428 for active balancing. The 1499's datasheet shows how to delay the 1499's active clamp signal via a CMOS inverter, which then drives the EMB1412 gate driver. The gate driver then drives the active clamping PMOS through the recommended level shifter.
My question is, my client's circuit has the PWM_CLP signal tied to the input of the CMOS inverter... BUT it's also tied directly to the gate driver's output!?
Your datasheet doesn't list the operating ranges for this signal, but merely mentions that it's a "logic" signal (i.e. not a gate driver), and so I'll guess that it's Iol/Ioh characteristics are limited to +/- 50mA. My understanding of this circuit is that, when the 1499 want's to turn the clamping FET on, it pulls (or attempts to) PWM_CLP low. But since the 1412's output is sitting HIGH, and is rated to source 3A (i.e. a strong pullup), it would appear that the PWM_CLP signal could NOT pull low, and would do so only AFTER it propagated through the delay inverter??
In other words, for the 300-400 ns delay period, you'd essentially have the 12V supply shorted through the 1412's pull-up FET and the 1499's pull-down FET.
Oh, and vice-versa: when the 1499 want's to turn the clamping FET off, it pulls (or attempts to) PWM_CLP high, but since the 1412's output is sitting LOW, and is rated to sink 7A (i.e. a strong pull-down), it would appear that the PWM_CLP signal could NOT pull high until it propagated through the delay inverter. So for 300-400 ns, you'd essentially have the 12V supply shorted through the 1412's pull-down FET and the 1499's pull-up FET.
The only potential "explanation" I can see is the comment in the datesheet: "The delay network should provide approximately 300ns to 400ns delay to the turn-on transition of the clamp PFET, and minimal delay to the turn-off transition."
This seems wrong to me, but my client says this circuit came directly from TI's original "Cheetah" reference design.
What am I missing?
Thanks in advance.
