Hi, team.
Please tell me the delay time from when an error is detected until ENDRV goes low.
Is it a logic delay only as shown in Fig.5-14?
Is there a part that is sampled and judged at a certain period?
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Hi, team.
Please tell me the delay time from when an error is detected until ENDRV goes low.
Is it a logic delay only as shown in Fig.5-14?
Is there a part that is sampled and judged at a certain period?
Hello Kobayashi-san,
The delay from a detected event that will impact ENDRV is essentially logic delay only, a couple of internal clock cycles plus a slight delay for the gate drive to turn the pull down FET for the open drain output on. This will be approximately 1us.