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TPS2331 Overcurrent Issues

Other Parts Discussed in Thread: TPS2331

I am debugging an inrush issue on a legacy design (circa 2007) which uses the TPS2331.  I have a few questions, issues:

1)  How is CTIMER reset when the current ceases to exceed the overcurrent threshold?  What would this time constant be (approximately) for CTIMER of 5.6nF?  I have an application in which the inrush current far exceeds the overcurrent threshold and I am unable to change the threshold and/or CTIMER because of the installed base of equipment.  The Inrush occurs on a controlled power on of a slave device after the TPS2331 500us fault hold-off.  I have demonstrated in the lab that if I pulse the power control to the slave device (approx 14us on, 3us off) the CTIMER voltage does not "accumulate" over multiple pulse periods suggesting that the discharge of CTIMER is less than 3us.

2)  In the same application, if I force an inrush of ~30A for ~50us and have a current limit of 30A, I "often, but not all the time" get the situation where the TPS2331 disables the pass FET after the 50us overcurrent timer (CTIMER is 5.6nF) BUT does not latch off.  This conflicts with the behaviour described in datasheet.  Approximately 200-400us later, the FET is re-enabled.  Subsequent over-current conditions as high a 60A for 100us do not cause CTIMER to charge and no fault is found.  Cycling the input power "resets" the TPS2331 and the next overcurrent cycle behaves properly.  Is there anything that could explain this behaviour?

3)  In approximately 1000 tested designs, operating over 3 years, we have had 4 cases where the TPS2331 has been destroyed during a power transient (confirmed in 2 cases to have occurred during loss of input power).  The "crater" in the package occurs nearest the pin 7/8 end of the TSSOP14.  I suspect that the only possible way this could happen is a high current surge through DISCH.  In the lab, I have recreated this (painfully):  in this case, the TPS2331 is connected to a booster design, the booster common node (inductor,diode,FET) was shorted to GND.  The 30AWG shorting wire melted indicating a high current for  a long duration.  I would have thought that the over current would have tripped, disconnected the input voltage and prevented damage ... if not to the wire than at least the TPS2331 should not have failed.  One could argue the 15uH inductor had something to do with it.... I guess.  But in the other 3 cases, this slave inductor was not present.  I have attached a schematic of my implementation.  Any thoughts as to the issue?

5775.SCH10001217_1V0_pg3.pdf

  • 1)  How is CTIMER reset when the current ceases to exceed the overcurrent threshold? 

    CTIMER is set by a current source. Comparators in the chip shut down the charging.

     What would this time constant be (approximately) for CTIMER of 5.6nF? 

    From the V, I relationship for a capacitor and a 50uA charge rate to 0.5V, I = C dv/dt, so T = C x V / I, T = (5.6nF x .5V)/50uA. = 56uS

    2)  In the same application, if I force an inrush of ~30A for ~50us and have a current limit of 30A, I "often, but not all the time" get the situation where the TPS2331 disables the pass FET after the 50us overcurrent timer (CTIMER is 5.6nF) BUT does not latch off.  This conflicts with the behaviour described in datasheet.  Approximately 200-400us later, the FET is re-enabled.  Subsequent over-current conditions as high a 60A for 100us do not cause CTIMER to charge and no fault is found.  Cycling the input power "resets" the TPS2331 and the next overcurrent cycle behaves properly.  Is there anything that could explain this behaviour?

    Do you have some decoupling like 0.1uF across the TPS2331? I wonder if voltage spiked down to 2.75V and it stayed in UVLO? Can the power supply hande these high test loads and inrush?

    the TPS2331 has been destroyed during a power transient (confirmed in 2 cases to have occurred during loss of input power).  The "crater" in the package occurs nearest the pin 7/8 end of the TSSOP14.

    The TPS2331 has a VIN Max of 13V. This isn't much overvoltage in a 12 V system especially a high current system where even small inductance in the input voltage can on either make or break create a voltage spike.

     

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    Bob Kando said:

    1)  How is CTIMER reset when the current ceases to exceed the overcurrent threshold? 

    CTIMER is set by a current source. Comparators in the chip shut down the charging.

     What would this time constant be (approximately) for CTIMER of 5.6nF? 

    From the V, I relationship for a capacitor and a 50uA charge rate to 0.5V, I = C dv/dt, so T = C x V / I, T = (5.6nF x .5V)/50uA. = 56uS

    JM -- I undertand how CTIMER is charged.  What I am trying to understand is how CTIMER is discharged when the fault is cleared.  It can't be simply "shutting down the charging" as I can clearly see the CTIMER votlage falling to zero much more quickly than the charge time (which is 56us).

    2)  In the same application, if I force an inrush of ~30A for ~50us and have a current limit of 30A, I "often, but not all the time" get the situation where the TPS2331 disables the pass FET after the 50us overcurrent timer (CTIMER is 5.6nF) BUT does not latch off.  This conflicts with the behaviour described in datasheet.  Approximately 200-400us later, the FET is re-enabled.  Subsequent over-current conditions as high a 60A for 100us do not cause CTIMER to charge and no fault is found.  Cycling the input power "resets" the TPS2331 and the next overcurrent cycle behaves properly.  Is there anything that could explain this behaviour?

    Do you have some decoupling like 0.1uF across the TPS2331? I wonder if voltage spiked down to 2.75V and it stayed in UVLO? Can the power supply hande these high test loads and inrush?

    JM -- The TP2331 Vin is decoupled with 0.1uF to GND (I attached my schematic to the original post).  In this particular test I am certain that Vin stayed at 12V (I had it on the scope too).  That wouldn't really explain why the TPS2331 returns to life but ignores subsequent overcurrent conditions.

    3) the TPS2331 has been destroyed during a power transient (confirmed in 2 cases to have occurred during loss of input power).  The "crater" in the package occurs nearest the pin 7/8 end of the TSSOP14.

    The TPS2331 has a VIN Max of 13V. This isn't much overvoltage in a 12 V system especially a high current system where even small inductance in the input voltage can on either make or break create a voltage spike.

    JM -- I can't say with any certainty that the main power supply did not exceed 13V, but I suspect it would not as it is generally well behaved and is spec'd at 12V +/- 5%.  It is capable of source 60A before it folds back.  I am not sure if the position of the crater is any indication as to what on the die overheated.  However, The main power supply is wired through about 12" of qty 24 of 18AWG wires, so there would be some very small input inductance.  I guess it is possible that if the TPS2331 shut down the FET properly (the current would have ceased) that Vin would have spiked above 13V due to the wire inductance flipping the voltage.  I guess that makes sense.

     

     

     

  • Ctimer is shorted with a FET