TINA/Spice/TPS3890: TPS3890 not giving the delay between MR and RESET based on CT value

haresh singh

Part Number: TPS3890
Other Parts Discussed in Thread: TINA-TI

Tool/software: TINA-TI or Spice Models

I am doing the the simulation in TINA with TPS389012 and TPS389033 to monitor multiple supply voltages of 1.2 and 3.3 as shown in the page no. 12(figure 23) of the data sheet. Spice models are taken from TI website.CT capacitor of 0.1uf (gives around 100ms delay) is put for bith the chips. 10K pull up is used at both chips reset pin. both 3.3 and 1.2 volt have slew time of 20ms.

when transient simulation is done the delay b/w MR(at 3.3 volt) and reset high of the 1.2 monitoring chip(TPS389012) is coming around 100 ms, but the,delay between MR high to reset high for the 3.3V monitoring chip(TPS389033) is only 5ms, which is not correct as per the data sheet(it should be ~100ms). Kindly help me out to solve the issue. Is it because spice model is not taking in to account of this case.

over 5 years ago

0 Michael_DeSando over 5 years ago

TI__Genius 12630 points

Haresh,

One thing you can try is to increase the slew rate at /MR pin as this pin is a digital input, not an analog input. The transition between logic low and logic high should be quick for /MR.

If this does not fix the issue, I will need to seek help from the TI modeling team that created the TINA spice model. They may be able to help you in figuring out why the model is not behaving as expected.

I have assigned the appropriate contact to help with the model. Please let us know if changing the slew rate fixed the issue. Thanks.

-Michael

0 Nikhil Gupta (Product Folder Models) over 5 years ago in reply to Michael_DeSando

TI__Mastermind 39210 points

Hi Haresh,

Please attach your TSC file so we can have a look at the issue.

0 haresh singh over 5 years ago in reply to Nikhil Gupta (Product Folder Models)

Prodigy 80 points

Kindly find the attached tsc file.

We want to confirm the delay between MR to reset for both the chips, as per the CT it should be ~100ms.reset ckt sim.TSC

0 haresh singh over 5 years ago

Prodigy 80 points

Changing the slew of MR is not helping I simulated

0 Nikhil Gupta (Product Folder Models) over 5 years ago in reply to haresh singh

TI__Mastermind 39210 points

Hi Haresh,

The model was built based on a preliminary version of the datasheet, which has slightly longer delays mentioned (see snippet below). The latest version of the datasheet has slightly faster delays.

Old datasheet (Preliminary)

Latest datasheet

I have adjusted the model to match 100ms that you require with the cap. If you want to fine tune this further, you can change the following line in the model:

G_U1_ABMI2 0 CT VALUE { IF(V(SENSE_CT)>0.5,1.5u,0) }

Increase the number 1.5u if you want to reduce the delay and decrease it if you want to increase the delay.

reset ckt sim_NG.TSC

0 haresh singh over 5 years ago in reply to Nikhil Gupta (Product Folder Models)

Prodigy 80 points

Thank you very much , by changing the 1.5u to 0.85 i am getting `~100ms delay between MR and reset.

Power management

Power management forum

TINA/Spice/TPS3890: TPS3890 not giving the delay between MR and RESET based on CT value