• State TI Thinks Resolved
  • Locked Locked
  • Replies 4 replies
  • Answers 1 answer
  • Subscribers 64 subscribers
  • Views 3761 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TPS53659: Skylake processor FIVR issue

Roy Chen52
Intellectual 395 points
Part Number: TPS53659

Dear Sir,

We found the VCCIO & PVCCIN turned off delay time was too long issue, causing short circuit of processor FIVR.

Is there a way to adjust the turn off shunt down rate(mv/us) with the GUI?

Thank you!

  • 0
    TI__Genius 11095 points

    Pin 13 of TPS53659 is u dual function pin. The default is to be an enable pin for Channel B. You may also configure Pin 13 to be a VCCIO Undervoltage monitoring pin. This selection is under MFR_SPECIFIC_00.

    When the TPS53659 detects VCCIO undervoltage, it will ramp the output voltage down actively to 0V at the rate specified by SetVID-Slow. 

  • 0 in reply to Matt Schurmann
    Intellectual 280 points

    Dear Sir,

    When Pin 10 (AVR_EN) drop before Pin 13 (connect to VCCIO), we found channel A output still can not shutdown rapidly, ever through VCCIO drop under 0.65V.

    But when Pin 10 keep high and Pin 13 drop firstly, Channel A output can shutdown rapidly.

    Is these the right reaction?

  • 0 in reply to Matt Schurmann
    Intellectual 395 points

    Dear Sir,

         After experiment, VCCIN can drop rapidly when "AVR_EN" keep high and "BEN_VCCIO" drop, but if "AVR_EN" drop before "BEN_VCCIO" drop, VCCIN will shutdown slowly,.
     Is it the right action?  In the normal system sequence, "AVR_EN" always  drop before(or the same time) VCCIO disable. We have tried connect "PG of VCCIO" to "AVR_EN"  and "BEN_VCCIO" to "VCCIO", but this connection still can not let VCCIN drop rapidly. Is there a suggested setting method?

    In addition， Here are two bring-up problem needs help.

    1. VR13 rail power down slew rate:
    According following Intel requirement, PVCCIN may need controlled ramp down rate. Could you help to confirm this feature?

    2.  We decode SVID comment and found two register can not be read from VR13 controller:  "03h data code" & "23h DC loadline".
            Are these two register available and necessary?

    Thank you!

      

  • 0 in reply to Roy Chen52
    TI__Genius 11095 points
    Hi Roy,

    #1- This is the expected behavior. The VR_EN pins will take priority, and cause a decay shutdown, if the VR_EN is de-asserted first. We are aware of the VCCIN requirement mentioned in #1. TPS53659 has a dedicated VCCIO UV pin in order to support it. TI chose to use a dedicated pin for VCCIO instead of enable soft-off through the VR_EN pins so that TPS53659 could flag VCCIO UV as a fault condition and notify the system. For the case where it is shared with enable, there is no way to tell the difference between normal VR_EN shutdown, and VCCIO UV. My suggestion would be to use the VCCIO pin as you shown in the experiment above, but delay the VCCIN VR_EN pin vs. the VCCIO VR_EN pin shutdown. This will allow VCCIN to ramp to ground as VCCIO decays, and also ensure VCCIO is fully established by the time VCCIN is enabled.

    #2- Yes, it is expected that TPS53659 will not respond to SVID GetReg for 0x23 (DCLL) and 0x03 (DATE_CODE). These are not mandatory registers and will not cause any issues if they are REJ.