Hi Sir,
The datasheet page 20 is show the Package outline TPS82085 is 2.7~2.9 x 2.9~3.1mm(2.8mmx3mm),
But page 21 EXAMPLE BOARD LAYOUT is 2.2+(0.5/2)*2=2.7mm Less than IC size, Is that correct?
Maybe have Insufficient Solder Risk?
Hugo
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Hi Sir,
The datasheet page 20 is show the Package outline TPS82085 is 2.7~2.9 x 2.9~3.1mm(2.8mmx3mm),
But page 21 EXAMPLE BOARD LAYOUT is 2.2+(0.5/2)*2=2.7mm Less than IC size, Is that correct?
Maybe have Insufficient Solder Risk?
Hugo