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CCS/UCD3138: About setting of UCD 3138

Part Number: UCD3138

Tool/software: Code Composer Studio


We have two questions.

We downloaded the code of this URLwww.ti.com/tool/ucd3138fw-psfbto UCD3138.

Although DPWM3A, 3B are observed, DPWM of 1B, 0B is not observed. What are the conditions for outputting DPWM of 1B, 0B?

Please tell me the range of voltage that can be output with UCD3138 and what happens to DPWM of 1B, 0B when setting outside the range.

 

best regards,

  • Looking at the code, I see that the sync FET is turned on and off depending on current:

    if (adc_values.io_sense > 460)   //Iout >6A
       {
        Dpwm0Regs.DPWMCTRL1.bit.GPIO_B_EN =0;
        Dpwm1Regs.DPWMCTRL1.bit.GPIO_B_EN =0;
       }
       else if (adc_values.io_sense < 250)   //Iout <3A
       {
        Dpwm0Regs.DPWMCTRL1.bit.GPIO_B_EN =1;
        Dpwm1Regs.DPWMCTRL1.bit.GPIO_B_EN =1;


    Setting the GPIO_B_EN bits will turn off the sync FET pins, because it makes them into general purpose I/O, taking control away from the DPWM.  So it looks like the Sync FETs are turned off when Iout goes below 3 A, and turned on when Iout goes above 6 A. 

    As far as voltage, the UCD3138 can control any voltage, so long as the monitoring and control voltages are stepped down to its 3.3 volt digital range, and its various analog ranges.  The PSFB board and software are designed to output 12 V.  If you get very far away from that, you will get a fault shutdown.  If you want a significantly different voltage, you would need a board redesign.  For the software, you would mostly just need to change filter coefficients, and lots of scaling, target, and limit constants to match the new design. 

  • Thank you for your reply

     The previous question was solved. However, We have new questions.

    What part of the code should be changed for the input current threshold?

    What is the requirement under which DPWM will phase shift?

    best regards,

  • I have one more question.

    When the output voltage is 0, DPWM is not observed.
    Are there any requirements for DPWM to occur?

    best regards,
  • I assume you are asking about the input current threshold at which the Peak Current mode switches the DPWMs off? If that is the question, here is what happens:

    1. Front End 0 (FE0) and Filter 0 are used for the voltage loop, which then sets a desired output current value into the EADCDAC in FE1.
    2. The error signal from FE1 is used as an input to Filter 1, which is the current loop (Iout).
    3. The output of Filter 1 is used as the starting point of the compensation ramp generated inside FE2, which is connected to primary side current.

    All this is done in hardware. So the input current threshold isn't really changed with code. You can change the relationship between the different signals - Vout, Iout, and Ipri, by changing the gains on the relative signals, either by changing the resistor values externally, or by changing the various scaling signals - KCOMP and the Filter Scaling bits - inside the UCD.

    The DPWM phase shifts when the peak current point where the primary current meets the compensation ramp at a different time.
  • Obviously, the output voltage will be 0 if no DPWM is running? I'm not sure what the question is.

    I can tell you what criteria are used to start the ramp up from the idle state. If you look at the idle_state_handler function in standard interrupt.c, you will see this line:

    else if (IOUT_NO_FAULT && VOUT_NO_FAULT && VIN_SUFFICIENT)//if Vin good

    Expanding it out will show you what criteria are used to start the ramp.

    There is a similar line of code in the ramp state handler.

    In the state for regulation, there are other criteria as well, including over temperature.