LM5575: Steady state vlue at pin SW (-1.5V).

Hello Jehan,

I believe that what you are asking what the meaning of “steady state” in the Abs Max table is. This statement allows this Abs Max specification to be violated for nanosecond pulses under extreme conditions as such max load cold and short circuit.

Regards, Robert

Yes, you are right. This is what i wanted to ask.  So this is my output at 0.8A

To be more precise

Further question is that, for how much of ns is ok? and what could be the maximum voltage that SW can handle?

regards

Hi Ambreesh

I have check the SW pin. Below are the results. So for 0.8A constant load current  i have a negative -5.66V for about 15ns. and this increases with the increase in load current. for 1A it goes as high as -6.8V. So my question is that for these negative voltages and for less than 50ns, the device will not have degradation effect?

regards

Jehan

Can you share the layout of the design ? . THe waveform looks OK to me and should not have any degradation effect .

Ambreesh

Jehan ,

There are few issues witht he layout that will impact the switch node ringing performance .

1. The input high di/dt loop is longer since the bypass cap is place far away from the VIn and the return path to PGND .
2. THe Sw node node trace is longer which will increase inductance and hence higher ringing .
3. THe Diode anode to the device is taken through vias whic again will increase inductance .

My recoomendation will be to reconsider the layout to minimioze the noise .

---Ambreesh

Thanks Ambreesh

Will consider your suggestions.

thanks