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BQ76200: discharge FETs fail short

Michael T Schneider
Expert 3790 points
Part Number: BQ76200

Hello Team,

We are using a BQ76200 Charge/Discharge High Side FET gate driver to control some charge/discharge FETs between a 28V Li-Ion battery cell stack and the external Battery output terminals.   Our configuration is similar to Figure 14 in the BQ76200 application note except that we are not using a Pre-charge FET.  We are also powering our Battery Management System with the node between charge and discharge FET drains.

We have had multiple discharge FETs fail short where it appears that the discharge FET gate is being damaged.  Charge FETs are not failing.  Recently, we have had some failures of this part where all of the Enable inputs (CHG_EN, CP_EN, DSG_EN, PMON-EN, and PCHG_EN) of the BQ76200 should have been pulled low when we connected the output of a DC power supply with the output disabled across the external terminals of the Battery.   The output of Power Supply that we connected to Battery external terminals may have had some residual voltage on output caps of Supply, but with FETs in off state, we didn’t think that would cause any issues with body diodes of Discharge FETs blocking path between Battery and external terminals.    We think that maybe there are some paths between Vpack, DSG, and/or ground pins in this IC that we don’t understand.   We were speculating that a transient negative voltage across the gate to source of the Discharge FETs might be causing discharge FET failures, but are not sure how this could happen when FETs should be in off state.

I was wondering if others using this part might have had similar issues and what the fixes might have been.   Any help or insights on the issues that we are having with this part would be appreciated

  • 0
    TI__Guru 54715 points
    Hi Michael,
    Your circuit may be similar to figure 14 of www.ti.com/.../slua794.pdf if that is the right application note. If the D2 zener is in place it is hard to imagine developing a large Vgs. Without the zener a step on the PACK+ could drop a large voltage across Rf and RDSG potentially stressing the FET Vgs limit. Triggering the ESD cell between DSG and PACK pins could also pull on the gate.
    One of the common problems encountered using the part is with a large Cf or too large of an RfCf time constant causing a failure to turn on or slow turn off resulting in discharge FET failure. It seems you are typically able to turn on however.
    In a recent experience a dynamic battery voltage caused a loss of the charge pump voltage and cut out of the CHG and DSG voltages. This was solved by decreasing the Cf and Cb capacitors so the device could better follow the dynamic battery voltage. That was a drop out experience rather than damage.
    These comments and the referenced apnote are the common guidance so I will mark this "thinks resolved", but please add component values or additional circuit details. Hopefully others will share their observations or experiences as you request also.