UCC28780: startup issue

Hello Gongsheng,

Thank you for your interest in the UCC28780 ACF controller.

To start the IC, the SWS input (which feeds the VDD pin internally at start-up) must rise to 17.5Vdc. This means that the source pin of the depletion-mode MOSFET must also reach 17.5V. 25V and higher on the Depl-FET drain should be able to start it.
If you measure only ~3V on the Depl-FET source, then something is holding down the voltage, maybe by diverting the start-up current away from the IC.

Only a few milliamps are needed to charge up the VDD capacitors (through SWS input). Please check the components on the SWS pin and on the VDD pin to see if any of them are loading down the nodes when the voltage rises to about ~3V.
For example, if you have some comparators or op-amps connected to VDD, they may draw sufficient current at 3V to prevent further charge up of the VDD caps.
If no extra components are connected, check the parts that are there to make sure they are not damaged and leaking (such as a cracked ceramic capacitor).

Does this help? If not, can you provide a schematic diagram (can be partial) of the UCC28780 controller portion of your system?

Regards,
Ulrich

Hello Gongsheng,

The UC28780 is designed for off-line AC to DC conversion control. Like most other off-line controllers, it is expected to be able to self-start when AC power is applied, without requiring an external source of bias power. So the off-line converter must generate its own bias power, as well as regulate the main output(s).

Deriving bias power continuously from the high voltage rectified bulk rail is very inefficient, so instead, an auxiliary winding provides the bias current at low voltage once the conversion is underway. But to start up, a very low current is used charge a VDD storage capacitor up to the turn-on threshold. The controller consumes a tiny current (a few uA) during the VDD charge-up phase, but then consumes many mA (for IC bias and for MOSFET gate drive) once switching begins.

The aux winding on the primary side of the transformer delivers the higher bias current at the IC bias voltage usually (but not necessarily) below the start-up threshold. However, this voltage only appears when the output voltage rises as the output capacitor(s) charge up. And it must be maintained above the controller's UVLO shut-down threshold (below which the IC cannot function).
This ramp up does not happen instantaneously, but may take several milliseconds, or tens of milliseconds to happen if there is a load on the output while it is trying to start up.

Now, if there was a low start threshold voltage close to the shutdown threshold, it would take an enormous VDD cap to store the charge needed to keep the IC functioning while the outputs ramp up and the aux winding voltage rises high enough above UVLO to sustain operation. To avoid requiring a huge capacitor, it is better to charge a smaller value up to a higher voltage. Once that voltage reaches the high start threshold, switching begins and the cap voltage begins to drop as power is being process to the output.

The VDD cap is sized such that the output voltage and consequently the Aux bias voltage rises high enough to keep the VDD above the UVLO level, before the cap voltage is depleted to the UVLO level. So a start threshold that is many volts higher than the UVLO shutdown threshold allows a much smaller cap to be used than if the start voltage were only ~1V above the shutdown threshold.

ICs that have a narrow start/stop range are usually intended for use in applications where a separate bias supply is already available before the main power conversion begins. Ironically, most often such a separate bias supply for the narrow-range IC is provided by an off-line controller with wide-range start-stop VDD, such as is being discussed in this post.

I hope this clarifies the reason for the 18-V start-up threshold on the UCC28780. It is unfortunate that the semiconductor process used for the gate-drive IC design imposes a relatively low limit on VDD that squeezes the range to accommodate both devices.

Regards,
Ulrich

Hello Gongsheng,

I am still travelling but I have a moment to address your questions which have accumulated. Starting with the schematic:

- My biggest concern is the capacitor on HVG, C64. It is shown as 100pF, but it should be 2~2.2nF. The HVG regulator needs it for stability to regulate the 11V on the Q5 gate. (This low cap value may have indirectly led to your earlier start-up issues.)

- My second concern is the 18V zener at D2, which should be a low-capacitance TVS (3~4pF) at 20~24V. A normal zener will add significant junction capacitance to the net and slow down the sensing of Vsw too much.

- Third is that the values for RDM and RTZ (R91 and R92 ) are calculated correctly. I can't check that because you do not provide any transformer information (Lm, Llk, Np, Ns, Na). You don't have to provide this, but please double check your calculations and use the most recent values for the equation factors. (Designers often change the values of various components during debug and forget to adjust other components whose proper values are dependent on the previously changed ones. Abnormal behavior may then occur.)

- Fourth is that the OPP adjustment resistor R94 is only 20 ohms. typical values are usually 50 to 100 times that, or more. However, I'm not sure what range it would be for a 30-80V input range. Still I think it would be higher than 20R. If the value is too low, then excess power can be delivered at high input voltage before OCP is triggered. If the value is too high then OCP kicks in too early at high line, and insufficient power is available.

Concerning the VDD hiccup:
The single PWML pulse at Vin = 20V is normal. This is a protection against an undetectable CS signal (if the input was shorted to GND, for instance). If the CS voltage does not rise to 0.28V within the time allowed by the SET setting (see datasheet page 35 on CS fault), the IC will conclude that CS is shorted and stop switching immediately after that first pulse. Your Vin = 20V is a condition such that the primary current cannot rise fast enough to meet this start-up criteria.
When Vin is higher at ~30V, CS-shorted fault is no longer detected, so more pulses are allowed. The should be at least three pulses (with hiccupping) after that until Vin is raised to the start-up threshold programmed by R95.
I don't know why you are getting only two. This seems abnormal, unless VDD is falling very quickly as these pulses occur so that UVLO is reached before the third pulse can happen.

Concerning the current peak (CS voltage) at 0.4V despite Vbur programmed at 0.2V:
This s most likely due to the driver propagation delay. If you display both PWML and LVG you can see the delay, which allows Ipk to go higher, even when PWML has gone low. The proper value of R94 (Ropp) will help mitigate the effect of this delay (and any others) for better Ipk control.

Using SET = 0V for a silicon MOSFET power stage may cause some subtle trouble, since the timing parameters for switching are affected. GaN FETs react much more quickly and have very low Coss, so the timing with SET = 0 is appropriate. High voltage Si-FETs are slower and SET = 5V provides better timing control.
However in your application, the 150-V FETs also have relatively low Coss, so the timing is relatively close that that for GaNs. It is hard to say if there will be significant trouble, but you may get better performance with one or the other. You may want to try both setting and compare. Refer to page 20 for details on the parameters that SET adjusts.
Leading-edge blanking time may be the parameter that gives you the most trouble, if it is too short.

I hope this helps you to bring up your system.

Regards,
Ulrich